Abstract: An example image forming apparatus includes a main body, a driving motor, a developing cartridge, and a clutch. The developing cartridge includes a toner container, a mounting portion to receive a toner refill cartridge, a toner inlet portion to connect the mounting portion to the toner container, and a toner inlet shutter to be switched between a blocking location for blocking the toner inlet portion and an inlet location for opening the toner inlet portion. The clutch is to selectively transmit a driving force of the driving motor to the toner inlet shutter.

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

Abstract: Techniques for reducing idle power consumption of a port are described herein. An example method includes determining device presence using a pull-down resistor disposed in a downstream port. The method also includes initiating a low power state of a link between the downstream port and an upstream device. The method also includes disabling the pull-down resistor in response to initiating the low power state.

Abstract: Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer that are compatible with a standard USB2 protocol. The link layer and protocol layer to control a physical layer for transmitting and receiving data on a pair of signal lines. The physical layer includes a fully-digital Low-Speed/Full-Speed (LS/FS) transceiver to transmit and receive data on the pair signal lines using single-ended digital communications on the pair of signal lines.

Abstract: For one disclosed embodiment, a controller comprises communication circuitry to communicate over one or more data lines with a downstream device external to an upstream device having the controller and detection circuitry to detect on at least one of the one or more data lines a voltage having a value in excess of a reference value. The detection circuitry is to deactivate a supply of power over one or more power lines to the downstream device in response to detection on at least one of the one or more data lines of a voltage having a value in excess of the reference value. Other embodiments are also disclosed.

Abstract: A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.

Abstract: Systems and methods for operating a universal serial bus are described herein. The method includes sending packet data from a USB2 device to a USB2 host on a pair of signal lines, and after sending the packet data, sending an End-Of-Packet (EOP) signal from the USB2 device to the USB2 host. The method also includes, entering the USB2 device into idle state after sending the EOP signal. The method also includes sending a digital ping from the USB2 device to the USB2 host to indicate device presence during idle state.

Abstract: Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer that are compatible with a standard USB2 protocol. The link layer and protocol layer to control a physical layer for transmitting and receiving data on a pair of signal lines. The physical layer includes a fully-digital Low-Speed/Full-Speed (LS/FS) transceiver to transmit and receive data on the pair signal lines using single-ended digital communications on the pair of signal lines.

Abstract: A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.

Abstract: Systems and methods for operating a universal serial bus are described herein. The method includes sending packet data from a USB2 device to a USB2 host on a pair of signal lines, and after sending the packet data, sending an End-Of-Packet (EOP) signal from the USB2 device to the USB2 host. The method also includes, entering the USB2 device into idle state after sending the EOP signal. The method also includes sending a digital ping from the USB2 device to the USB2 host to indicate device presence during idle state.

Abstract: A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.

Abstract: A method for explicit control message signaling includes sending a single ended 1 signal on a pair of data lines, wherein the pair of data lines includes a first data line and a second data line. A voltage of the first data line is driven to a logic 1, while pulsing the voltage of the second data line between a logic 1 and a logic 0, wherein the pulses represent a control message.

Abstract: A method for explicit control message signaling includes sending a single ended 1 signal on a pair of data lines, wherein the pair of data lines includes a first data line and a second data line. A voltage of the first data line is driven to a logic 1, while pulsing the voltage of the second data line between a logic 1 and a logic 0, wherein the pulses represent a control message.

Abstract: Systems and methods for detecting Input/Output (I/O) device connection are described herein. The method includes physically coupling an I/O device to a host port through a first signal line and a second signal line. The method also includes driving the first signal line or the second signal line high via an active buffer of the I/O device. The method also includes providing an acknowledgement signal from the host to the device through the other signal line that is not being driven high by the active buffer of the I/O device.

Abstract: Techniques for reducing idle power consumption of a port are described herein. An example method includes determining device presence using a pull-down resistor disposed in a downstream port. The method also includes initiating a low power state of a link between the downstream port and an upstream device. The method also includes disabling the pull-down resistor in response to initiating the low power state.

Abstract: Systems and methods for operating a universal serial bus are described herein. The method includes sending packet data from a USB2 device to a USB2 host on a pair of signal lines, and after sending the packet data, sending an End-Of-Packet (EOP) signal from the USB2 device to the USB2 host. The method also includes, entering the USB2 device into idle state after sending the EOP signal. The method also includes sending a digital ping from the USB2 device to the USB2 host to indicate device presence during idle state.

Abstract: A method for detecting device disconnect in a repeater is disclosed herein. The method includes receiving a disconnect indication comprising a voltage swing occurring on a data channel for a peripheral device. The method also includes receiving a start-of-frame indication that indicates that a threshold consecutive number of bits of the same data value has been received. The method further includes sending a device disconnect message to a host based on the disconnect indication and the start-of-frame indication.