Abstract: A method and apparatus for determining and recovering from a USB micro-controller busy condition, wherein a toggle variable indicative of whether the USB micro-controller is in the busy condition or not is stored in a memory, and a counter is incremented if the toggle variable is set. The counter is checked to determine if the counter has reached a predetermined count, and if so data lines of the USB micro-controller are disconnected from a USB bus coupled to the USB micro-controller for a predetermined amount of time to cause a USB host computer coupled to the USB micro-controller to re-initialize the USB micro-controller. The memory contains a data structure including fields for storing the toggle variable, and a count indicative of how many times the toggle variable has been set for implementing the counter.

Abstract: A memory controller is disclosed for use in physically mapping a VESA Unified Memory Architecture (VUMA) device, Row Address Strobe signal RAS# to a selected one of a plurality of memory banks. The RAS# signal from the VUMA device is routed to the memory controller, not the memory bank directly. The memory controller employs a network of pass gates to provide an electrically-conductive channel for routing the VUMA device RAS# signal to the appropriate memory bank. The appropriate pass gate is caused to become conductive through the use of a decoder, and a 3-bit clocked register bank. The register bank is programmable to generate a select signal on its output that is representative of the desired memory bank to receive the VUMA device RAS# signal. The select signal, which is a 3-bit signal, is provided to the decoder, which activates one of its plurality of output lines to thereby cause the selected pass gate to conduct.

Abstract: The present invention provides power saving features that can be used in a computer or other device employing an internal clock to dynamically change the frequency at which the clock operates to respond to demands upon system resources. For example, the CPU clock in the synchronous logic core may be changed dynamically to reduce power consumption without causing a CPU lock-up. A PLL clock internal to the CPU has a reduced sensitivity to external clock changes. The present invention provides a means to incrementally change the internal clock frequency by intermittently stopping the output of the internal clock.

Abstract: The present invention provides a device for terminating a data bus. The present invention provides the proper termination without the use of external discrete components. The device can be programmed, at the chip level, to produce particular termination resistances that are commonly used. The present invention termination device uses a minimum of power dissipation which may be useful in applications that require minimum power consumption.