Patents by Inventor Kok Khoon Ho
Kok Khoon Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220028813Abstract: A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Applicant: Semtech CorporationInventors: Kok Khoon Ho, Jonathan Clark, John MacLeod
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Patent number: 11171099Abstract: A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.Type: GrantFiled: July 29, 2019Date of Patent: November 9, 2021Assignee: Semtech CorporationInventors: Kok Khoon Ho, Jonathan Clark, John MacLeod
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Publication number: 20190355689Abstract: A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.Type: ApplicationFiled: July 29, 2019Publication date: November 21, 2019Applicant: Semtech CorporationInventors: Kok Khoon Ho, Jonathan Clark, John MacLeod
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Patent number: 10410988Abstract: A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.Type: GrantFiled: August 4, 2017Date of Patent: September 10, 2019Assignee: Semtech CorporationInventors: Kok Khoon Ho, Jonathan Clark, John MacLeod
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Patent number: 9899285Abstract: A semiconductor device has a plurality of first semiconductor die. A plurality of first bumps is formed over the first semiconductor die. A first protection layer is formed over the first bumps. A portion of the first semiconductor die is removed in a backgrinding operation. A backside protection layer is formed over the first semiconductor die. An encapsulant is deposited over the first semiconductor die and first bumps. A portion of the encapsulant is removed to expose the first bumps. A conductive layer is formed over the first bumps and encapsulant. An insulating layer and plurality of second bumps are formed over the conductive layer. A plurality of conductive vias is formed through the encapsulant. A plurality of the semiconductor devices is stacked with the conductive vias electrically connecting the stacked semiconductor devices. A second semiconductor die having a through silicon via is disposed over the first semiconductor die.Type: GrantFiled: July 30, 2015Date of Patent: February 20, 2018Assignee: Semtech CorporationInventors: Kok Khoon Ho, Satyamoorthi Chinnusamy
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Publication number: 20180047688Abstract: A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.Type: ApplicationFiled: August 4, 2017Publication date: February 15, 2018Applicant: Semtech CorporationInventors: Kok Khoon Ho, Jonathan Clark, John MacLeod
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Semiconductor device and method of forming DCALGA package using semiconductor die with micro pillars
Patent number: 9875988Abstract: A semiconductor device has a first semiconductor die disposed over a substrate. A plurality of composite interconnect structures are formed over the semiconductor die. The composite interconnect structures have a non-fusible conductive pillar and a fusible layer formed over the non-fusible conductive pillar. The fusible layer is reflowed to connect the first semiconductor die to a conductive layer of the substrate. The non-fusible conductive pillar does not melt during reflow eliminating a need to form a solder resist over the substrate. An encapsulant is deposited around the first semiconductor die and composite interconnect structures. The encapsulant flows between the active surface of the first semiconductor die and the substrate. A second semiconductor die is disposed over the substrate adjacent to the first semiconductor die. A heat spreader is disposed over the first semiconductor die. A portion of the encapsulant is removed to expose the heat spreader.Type: GrantFiled: October 29, 2015Date of Patent: January 23, 2018Assignee: Semtech CorporationInventors: Satyamoorthi Chinnusamy, Weng Hing Tan, Andrew Pan, Kok Khoon Ho -
Publication number: 20170133323Abstract: A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die.Type: ApplicationFiled: January 25, 2017Publication date: May 11, 2017Applicant: Semtech CorporationInventors: Kok Khoon Ho, Satyamoorthi Chinnusamy
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Semiconductor Device and Method of Forming DCALGA Package Using Semiconductor Die with Micro Pillars
Publication number: 20170125375Abstract: A semiconductor device has a first semiconductor die disposed over a substrate. A plurality of composite interconnect structures are formed over the semiconductor die. The composite interconnect structures have a non-fusible conductive pillar and a fusible layer formed over the non-fusible conductive pillar. The fusible layer is reflowed to connect the first semiconductor die to a conductive layer of the substrate. The non-fusible conductive pillar does not melt during reflow eliminating a need to form a solder resist over the substrate. An encapsulant is deposited around the first semiconductor die and composite interconnect structures. The encapsulant flows between the active surface of the first semiconductor die and the substrate. A second semiconductor die is disposed over the substrate adjacent to the first semiconductor die. A heat spreader is disposed over the first semiconductor die. A portion of the encapsulant is removed to expose the heat spreader.Type: ApplicationFiled: October 29, 2015Publication date: May 4, 2017Applicant: Semtech CorporationInventors: Satyamoorthi Chinnusamy, Weng Hing Tan, Andrew Pan, Kok Khoon Ho -
Patent number: 9601461Abstract: A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die.Type: GrantFiled: August 12, 2015Date of Patent: March 21, 2017Assignee: Semtech CorporationInventors: Kok Khoon Ho, Satyamoorthi Chinnusamy
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Publication number: 20170047308Abstract: A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die.Type: ApplicationFiled: August 12, 2015Publication date: February 16, 2017Applicant: SEMTECH CORPORATIONInventors: Kok Khoon Ho, Satyamoorthi Chinnusamy
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Publication number: 20170033026Abstract: A semiconductor device has a plurality of first semiconductor die. A plurality of first bumps is formed over the first semiconductor die. A first protection layer is formed over the first bumps. A portion of the first semiconductor die is removed in a backgrinding operation. A backside protection layer is formed over the first semiconductor die. An encapsulant is deposited over the first semiconductor die and first bumps. A portion of the encapsulant is removed to expose the first bumps. A conductive layer is formed over the first bumps and encapsulant. An insulating layer and plurality of second bumps are formed over the conductive layer. A plurality of conductive vias is formed through the encapsulant. A plurality of the semiconductor devices is stacked with the conductive vias electrically connecting the stacked semiconductor devices. A second semiconductor die having a through silicon via is disposed over the first semiconductor die.Type: ApplicationFiled: July 30, 2015Publication date: February 2, 2017Applicant: SEMTECH CORPORATIONInventors: Kok Khoon Ho, Satyamoorthi Chinnusamy
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Patent number: 6547121Abstract: An apparatus is provided wherein a substrate is mechanically clamped to a heater block of a die bonder to hold down the heated substrate before and during the die bonding operation, thereby preventing warpage of the substrate. Embodiments include a clamp comprising a plurality of spring-loaded rollers which push down opposing outer edges of the substrate onto the heater block while the substrate is being heated and die bonded. The clamp minimizes warpage of the substrate by pushing the substrate flat onto the heater block, and allows the substrate to be moved into and away from the die bonding area.Type: GrantFiled: January 19, 2001Date of Patent: April 15, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Sally Y. L. Foong, Kok Khoon Ho
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Publication number: 20020106603Abstract: An apparatus is provided wherein a substrate is mechanically clamped to a heater block of a die bonder to hold down the heated substrate before and during the die bonding operation, thereby preventing warpage of the substrate. Embodiments include a clamp comprising a plurality of spring-loaded rollers which push down opposing outer edges of the substrate onto the heater block while the substrate is being heated and die bonded. The clamp minimizes warpage of the substrate by pushing the substrate flat onto the heater block, and allows the substrate to be moved into and away from the die bonding area.Type: ApplicationFiled: January 19, 2001Publication date: August 8, 2002Applicant: Advanced Micro Devices, Inc.Inventors: Sally Y. L. Foong, Kok Khoon Ho
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Patent number: 6383843Abstract: A method is provided for die bonding a semiconductor device to a substrate, which method provides adequate and consistent bondline thickness and assures that the die is spaced from the substrate a predetermined amount. Embodiments include removably attaching a flexible spacer of a predetermined thickness, such as a strip of paper or plastic, to the bonding pad of a substrate, such as an organic lead frame, so that it partially covers the bonding pad while leaving other parts of the bonding pad exposed. Die attach material, such as epoxy paste, is then applied to the exposed areas of the bonding pad, and a die is placed over the bonding pad in contact with the epoxy and the spacer. Due to the presence of the spacer, the die cannot sink when it is placed on the epoxy paste, resulting in a consistent bondline thickness equal to the spacer thickness.Type: GrantFiled: April 17, 2000Date of Patent: May 7, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Sally Y. L. Foong, Kok Khoon Ho