Abstract: The present systems and methods extend the frequency range of a clock signal generated with a phase-locked loop (PLL). The PLL receives a reference signal from a reference signal divider and a feedback signal from a feedback signal divider. The PLL generates an output signal that is forwarded to a programmable divider. The programmable divider includes control logic, core logic, and post-processing logic. The control logic synchronizes signals distributed throughout the system to prevent metastability. The core logic generates a divide-by-N waveform that is forwarded to the post-processing logic. The post-processing logic generates a half duty cycle clock signal responsive to the divide-by-N waveform.