Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces attic upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Abstract: Systems and methods are disclosed for forming a custom integrated circuit (IC) with a first fixed (non-programmable) region on a wafer with non-customizable mask layers, wherein the first fixed region includes multiplicities of transistors and a first interconnect layer and a second interconnect layer above the first interconnect layer which form base cells; and a programmable region above the first fixed region with customizable mask layers, wherein at least one mask layer in the programmable region is coupled to the second interconnect layer which provides electrical access to all transistor nodes of the base cells and wherein the programmable region comprises a third interconnect layer coupled to the customizable mask layers to customize the IC. A second fixed region may be formed above the programmable region to provide multiple fixed regions and reduce the number of required masks in customizing the custom IC.

Abstract: Systems and methods are disclosed for forming a custom integrated circuit (IC) with a first fixed (non-programmable) region on a wafer with non-customizable mask layers, wherein the first fixed region includes multiplicities of transistors and a first interconnect layer and a second interconnect layer above the first interconnect layer which form base cells; and a programmable region above the first fixed region with customizable mask layers, wherein at least one mask layer in the programmable region is coupled to the second interconnect layer which provides electrical access to all transistor nodes of the base cells and wherein the programmable region comprises a third interconnect layer coupled to the customizable mask layers to customize the IC. A second fixed region may be formed above the programmable region to provide multiple fixed regions and reduce the number of required masks in customizing the custom IC.

Abstract: Hotsocket detection circuitry is provided for detecting hotsocket conditions in integrated circuits such as programmable logic device integrated circuits. Power-on-reset circuitry may provide a power-on-reset signal that is indicative of when power supply voltages are ready to power circuitry on the integrated circuit for normal operation. A delay circuit that is powered by a power supply voltage may receive the power-on-reset signal and may generate a corresponding delayed version of the power-on-reset signal. The delayed version of the power-on-reset signal may be provided to the hotsocket detection circuitry to ensure that the hotsocket detection circuitry produces a hotsocket signal that transitions after a transition in the power-on-reset signal. The delay circuit may include one or more inverter stages.

Abstract: An adjustable level shifter with native and kicker transistors is provided. The level shifter provides high switching speeds, adjustable output voltage levels, and low jitter. The level shifter has first and second thick-oxide p-channel metal-oxide-semiconductor (PMOS) transistors, first and second thick-oxide native n-channel metal-oxide-semiconductor (NMOS) transistors, and first and second thin-oxide NMOS transistors. The first PMOS transistor, first native transistor, and first NMOS transistor are connected in series and the second PMOS transistor, second native transistor, and second NMOS transistor are connected in series. An input data signal and an inverted version of the input data signal drive the gates of the thin-oxide NMOS transistors. A node located between the first PMOS transistor and first native transistor is connected to an output data terminal. The kicker transistor is connected in parallel with the first PMOS transistor.