Patents by Inventor Kok-Soon Yeo

Kok-Soon Yeo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11664719
    Abstract: During a first mode of operation, a zero current detect (ZCD) signal is asserted in response to detecting a zero current condition at a switch node of a power converter. The power converter enters a light load mode of operation when the ZCD signal is asserted between a beginning point and a trigger point of a period of a PWM signal. A compensator voltage is generated based on a feedback voltage indicative of an output voltage. The compensator voltage is compared to a threshold voltage that represents a limit for the compensator voltage during the light load mode of operation determined over a range of the output voltage. The power converter exits the light load mode back to the first mode of operation in response to the compensator voltage being beyond the threshold voltage.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 30, 2023
    Assignee: Silanna Asia Pte Ltd
    Inventors: Rawinder Dharmalinggam, Kais Badami, Kok Soon Yeo
  • Publication number: 20210006165
    Abstract: During a first mode of operation, a zero current detect (ZCD) signal is asserted in response to detecting a zero current condition at a switch node of a power converter. The power converter enters a light load mode of operation when the ZCD signal is asserted between a beginning point and a trigger point of a period of a PWM signal. A compensator voltage is generated based on a feedback voltage indicative of an output voltage. The compensator voltage is compared to a threshold voltage that represents a limit for the compensator voltage during the light load mode of operation determined over a range of the output voltage. The power converter exits the light load mode back to the first mode of operation in response to the compensator voltage being beyond the threshold voltage.
    Type: Application
    Filed: August 3, 2020
    Publication date: January 7, 2021
    Applicant: Silanna Asia Pte Ltd
    Inventors: Rawinder Dharmalinggam, Kais Badami, Kok Soon Yeo
  • Patent number: 10763738
    Abstract: During a first mode of operation, a zero current detect (ZCD) signal is asserted in response to detecting a zero current condition at a switch node of a power converter. The power converter enters a light load mode of operation when the ZCD signal is asserted between a beginning point and a trigger point of a period of a PWM signal. A compensator voltage is generated based on a feedback voltage indicative of an output voltage. The compensator voltage is compared to a threshold voltage that represents a limit for the compensator voltage during the light load mode of operation determined over a range of the output voltage. The power converter exits the light load mode back to the first mode of operation in response to the compensator voltage being beyond the threshold voltage.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: September 1, 2020
    Assignee: Silanna Asia Pte Ltd
    Inventors: Rawinder Dharmalinggam, Kais Badami, Kok Soon Yeo
  • Patent number: 7570109
    Abstract: A system and method for demodulating amplitude modulated input signals uses two comparators and a charge pump circuit, which is positioned between the two comparators, to produce a demodulated signal of an amplitude modulated input signal. The two comparators and the charge pump circuit form a demodulating unit that may be a part of an infrared remote control receiver. The first comparator converts the input signal from a waveform to a pulse form. The charge pump circuit then converts the pulse signal into an integrated signal in a triangular pulse form. The second comparator converts the integrated signal from a triangular pulse form to a rectangular pulse form to produce the demodulated signal.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: August 4, 2009
    Assignee: Lite-On Technology Corp.
    Inventors: Lian-Chun Xu, Kok-Soon Yeo, Chee-Keong Teo, John Julius Asuncion, Wai Keat Tai
  • Patent number: 7561812
    Abstract: An optical receiver has a voltage supply, a first node, and a second node. A first input of a differential amplifier is coupled to the first node and a second input of the differential amplifier is coupled to the second node. A photodetector is coupled between the voltage supply and the first node, which produces a photodetector capacitance. A programmable variable capacitor having a capacitance selectively matched to the photodetector capacitance is coupled between the voltage supply and the second node.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: July 14, 2009
    Assignee: Lite-On Technology Corp.
    Inventors: Wai Keat Tai, Kok Soon Yeo, Chee Keong Teo, John Julius Asuncion, Lian Chun Xu
  • Patent number: 7511567
    Abstract: A reference voltage circuit includes first circuitry that generates a thermal voltage that is approximately proportional to absolute temperature, a first voltage multiplier, second circuitry that generates an inverse thermal voltage that is approximately inversely proportional to absolute temperature, a second voltage multiplier and a summer. The first voltage multiplier multiplies the thermal voltage to obtain a first multiplied voltage. The multiplied voltage is not equal to the thermal voltage. The second voltage multiplier multiplies the inverse thermal voltage to obtain a second multiplied voltage. The summer sums the first multiplied voltage with the second multiplied voltage to obtain a reference voltage.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: March 31, 2009
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Kok-Soon Yeo, Wai-Keat Tai
  • Patent number: 7309852
    Abstract: In one embodiment, an optical transducer, such as an infrared transducer, generates an output signal that is representative of optical irradiance. A noise control circuit is coupled in a power supply path of the optical transducer. A switching circuit varies the noise control provided by the noise control circuit, in response to changes in the output signal of the optical transducer. The noise control may be varied in a number of different ways, including: turning the noise control on or off, varying the noise control in discrete steps, or varying the noise control in a continuous manner. Methods for varying noise control in response to optical irradiance of an optical transducer are also disclosed.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: December 18, 2007
    Assignee: Avago Technologies ECBU IP (Singapore) Pte Ltd.
    Inventors: Kok-Soon Yeo, Lian-Chun Xu, Chee-Keong Teo, John Julius De Leon Asuncion
  • Publication number: 20070205826
    Abstract: A system and method for demodulating amplitude modulated input signals uses two comparators and a charge pump circuit, which is positioned between the two comparators, to produce a demodulated signal of an amplitude modulated input signal. The two comparators and the charge pump circuit form a demodulating unit that may be a part of an infrared remote control receiver. The first comparator converts the input signal from a waveform to a pulse form. The charge pump circuit then converts the pulse signal into an integrated signal in a triangular pulse form. The second comparator converts the integrated signal from a triangular pulse form to a rectangular pulse form to produce the demodulated signal.
    Type: Application
    Filed: November 4, 2005
    Publication date: September 6, 2007
    Inventors: Lian-Chun Xu, Kok-Soon Yeo, Chee-Keong Teo, John Asuncion, Wai Tai
  • Patent number: 7265626
    Abstract: A fast-settling digital automatic gain control circuit comprises first and second gain-controllable amplifiers in series. Each amplifier can be digitally switched between minimum and maximum gains by control logic that receives inputs from a multi-level voltage comparator. A peak detector connected to the output of the first gain-controlled amplifier is used to set the overall operating ranges for several threshold detectors. Four reference voltages are generated from the peak detector. The highest reference voltage is used to clock and reset the gain control logic with a hysteresis comparator to the instantaneous input signal from the first gain-controlled amplifier. The three other lower reference voltages are used to provide three-bits of digital input data to the gain control logic. Two digital controls are output, a min/max gain bit for the first gain-controlled amplifier, and a similar min/max gain bit for the second gain-controlled amplifier.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: September 4, 2007
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Chee Keong Teo, Lian-Chun Xu, Kok-Soon Yeo, John Julius Asuncion, Wai Keat Tai
  • Publication number: 20070139118
    Abstract: A fast-settling digital automatic gain control circuit comprises first and second gain-controllable amplifiers in series. Each amplifier can be digitally switched between minimum and maximum gains by control logic that receives inputs from a multi-level voltage comparator. A peak detector connected to the output of the first gain-controlled amplifier is used to set the overall operating ranges for several threshold detectors. Four reference voltages are generated from the peak detector. The highest reference voltage is used to clock and reset the gain control logic with a hysteresis comparator to the instantaneous input signal from the first gain-controlled amplifier. The three other lower reference voltages are used to provide three-bits of digital input data to the gain control logic. Two digital controls are output, a min/max gain bit for the first gain-controlled amplifier, and a similar min/max gain bit for the second gain-controlled amplifier.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Inventors: Chee Teo, Lian-Chun Xu, Kok-Soon Yeo, John Asuncion, Wai Tai
  • Patent number: 7220953
    Abstract: A circuit has a voltage source, a node, a photodetector electrically coupled between the voltage source and the node, a resistor electrically coupled between the node and ground, and a voltage clamp electrically connected to the node, the voltage clamp configured to maintain a reverse bias of the photodetector above a predetermined level.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: May 22, 2007
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Chee Keong Teo, John Julius Asuncion, Kok Soon Yeo, Lian Chun Xu, Wai Keat Tal
  • Patent number: 7215151
    Abstract: A multi-stage light emitting diode (LED) driver circuit is provided. The circuit includes a driver transistor coupled to an LED. The LED is coupled at a drain of the driver transistor and the driver transistor drives current to the LED. A first transistor stack is coupled between a gate of the driver transistor and ground. A first inverter stage is coupled to a common gate of the first transistor stack. The first inverter stage is further coupled between a high voltage source and ground. A second inverter stage is coupled to a common gate of the first inverter stage. The second inverter stage is further coupled between the high voltage source and ground. The circuit further includes a first transistor coupled between the high voltage source and gate of the driver transistor. The gate of the transistor is coupled to the first inverter stage.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: May 8, 2007
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Wai Keat Tai, Kok-Soon Yeo, Chee-Keong Teo, John J. De Leon Asuncion, Lian-Chun Xu
  • Publication number: 20070080741
    Abstract: A reference voltage circuit includes first circuitry that generates a thermal voltage that is approximately proportional to absolute temperature, a first voltage multiplier, second circuitry that generates an inverse thermal voltage that is approximately inversely proportional to absolute temperature, a second voltage multiplier and a summer. The first voltage multiplier multiplies the thermal voltage to obtain a first multiplied voltage. The multiplied voltage is not equal to the thermal voltage. The second voltage multiplier multiplies the inverse thermal voltage to obtain a second multiplied voltage. The summer sums the first multiplied voltage with the second multiplied voltage to obtain a reference voltage.
    Type: Application
    Filed: October 6, 2005
    Publication date: April 12, 2007
    Inventors: Kok-Soon Yeo, Wai-Keat Tai
  • Patent number: 7187223
    Abstract: In one embodiment, a comparator is provided with a first differential input stage that receives an input voltage and a reference voltage and produces a first differential output, and a second differential input stage that has differential inputs and produces a second differential output. A comparator stage produces a comparator output in response to the first and second differential outputs. The comparator also has a hysteresis control circuit, the components of which include 1) a resistor and a hysteresis regulating voltage input, coupled between the differential inputs of the second differential input stage, 2) first and second current generators, and 3) at least one switch, under control of the comparator output, to alternately enable different combinations of the first and second current generators, thereby inducing a first or a second current through the resistor.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: March 6, 2007
    Assignee: Avago Technologies ECBU (IP) Singapore Pte. Ltd.
    Inventors: Kok-Soon Yeo, Lian-Chun Xu, Chee-Keong Teo, John Julius de Leon Asuncion, Wai-Keat Tai
  • Publication number: 20070040543
    Abstract: A bandgap circuit includes a current mirror that generates a proportional to absolute temperature current at an output node that outputs the bandgap reference voltage. A first current path including a first resistor is coupled between the output node and a first bipolar transistor. The second current path including a second resistor is coupled between the output node and a second bipolar transistor. The first current path is parallel to the second current path. The circuit outputs a bandgap reference voltage.
    Type: Application
    Filed: August 16, 2005
    Publication date: February 22, 2007
    Inventors: Kok-Soon Yeo, Lian-Chun Xu, Wai Tai, Chee-Keong Teo, John Asuncion
  • Publication number: 20070018685
    Abstract: A multi-stage light emitting diode (LED) driver circuit is provided. The circuit includes a driver transistor coupled to an LED. The LED is coupled at a drain of the driver transistor and the driver transistor drives current to the LED. A first transistor stack is coupled between a gate of the driver transistor and ground. A first inverter stage is coupled to a common gate of the first transistor stack. The first inverter stage is further coupled between a high voltage source and ground. A second inverter stage is coupled to a common gate of the first inverter stage. The second inverter stage is further coupled between the high voltage source and ground. The circuit further includes a first transistor coupled between the high voltage source and gate of the driver transistor. The gate of the transistor is coupled to the first inverter stage.
    Type: Application
    Filed: July 22, 2005
    Publication date: January 25, 2007
    Inventors: Wai Tai, Kok-Soon Yeo, Chee-Keong Teo, John De Leon Asuncion, Lian-Chun Xu
  • Publication number: 20060181314
    Abstract: In one embodiment, a comparator is provided with a first differential input stage that receives an input voltage and a reference voltage and produces a first differential output, and a second differential input stage that has differential inputs and produces a second differential output. A comparator stage produces a comparator output in response to the first and second differential outputs. The comparator also has a hysteresis control circuit, the components of which include 1) a resistor and a hysteresis regulating voltage input, coupled between the differential inputs of the second differential input stage, 2) first and second current generators, and 3) at least one switch, under control of the comparator output, to alternately enable different combinations of the first and second current generators, thereby inducing a first or a second current through the resistor.
    Type: Application
    Filed: February 14, 2005
    Publication date: August 17, 2006
    Inventors: Kok-Soon Yeo, Lian-Chun Xu, Chee-Keong Teo, John Julius de Asuncion, Wai-Keat Tai
  • Publication number: 20060081779
    Abstract: In one embodiment, an optical transducer, such as an infrared transducer, generates an output signal that is representative of optical irradiance. A noise control circuit is coupled in a power supply path of the optical transducer. A switching circuit varies the noise control provided by the noise control circuit, in response to changes in the output signal of the optical transducer. The noise control may be varied in a number of different ways, including: turning the noise control on or off, varying the noise control in discrete steps, or varying the noise control in a continuous manner. Methods for varying noise control in response to optical irradiance of an optical transducer are also disclosed.
    Type: Application
    Filed: October 18, 2004
    Publication date: April 20, 2006
    Inventors: Kok-Soon Yeo, Lian-Chun Xu, Chee-Keong Teo, John Asuncion
  • Patent number: 6812778
    Abstract: A compensating circuit for providing a compensating control signal to a regulating circuit is provided. The compensating circuit includes a multiplying circuit and a miller capacitor. The multiplying circuit may provide a predetermined multiplication factor to a miller current level based on a resistor ratio. The multiplying circuit may also provide a voltage gain stage before the miller capacitor. Both multiplying circuits enable the size of the miller capacitor to be reduced resulting in valuable printed circuit board space savings.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: November 2, 2004
    Assignee: 02Micro International Limited
    Inventors: Kok Soon Yeo, Ai min Xu, Hong Meng Joel Tang