Patents by Inventor Kok Tjoan Lie

Kok Tjoan Lie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9727982
    Abstract: A method of compositing layers by grouping the layers into a foreground group and a background group; identifying independent instructions of compositing model for execution independently from the background group and dependent instructions requiring a compositing output of a background layer in order to composite foreground layers; executing the independent instructions on the foreground layers in parallel with compositing the background layers, a first independent instruction storing a corresponding result in a first buffer and a second independent instruction storing a corresponding result in a second buffer; executing a dependent instruction by updating the second buffer using the background compositing output; and determining a compositing output for the foreground group dependent upon contents of the first buffer and the updated second buffer.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 8, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Zhi-Min Pan, David Ian Johnston, Gregory Joseph Johnson, Kok Tjoan Lie
  • Publication number: 20160328633
    Abstract: A method of compositing layers by grouping the layers into a foreground group and a background group; identifying independent instructions of compositing model for execution independently from the background group and dependent instructions requiring a compositing output of a background layer in order to composite foreground layers; executing the independent instructions on the foreground layers in parallel with compositing the background layers, a first independent instruction storing a corresponding result in a first buffer and a second independent instruction storing a corresponding result in a second buffer; executing a dependent instruction by updating the second buffer using the background compositing output; and determining a compositing output for the foreground group dependent upon contents of the first buffer and the updated second buffer.
    Type: Application
    Filed: May 3, 2016
    Publication date: November 10, 2016
    Inventors: Zhi-Min PAN, David Ian JOHNSTON, Gregory Joseph JOHNSON, Kok Tjoan LIE
  • Patent number: 6828985
    Abstract: Disclosed are methods, apparatus (1) and computer readable media for rendering at least one graphic object (80, 90) described by at least one edge (82-86, 92-98) into a raster pixel image (78) having a plurality of scan lines and a plurality of pixel locations on each scan line. For each scan line, coordinates of intersection of those edges of the objects that intersect the scan line are determined in a predetermined order. This is preferably achieved by processing edge records (418) using a number of buffers (402, 404, 406, 412, 420, 422) thereby enabling efficient sorting of edge intersections into order. For each adjacent pair of edge intersections, information (530) associated with the corresponding object is examined to determining a set of active objects (508, 510) for a span of pixel locations between the corresponding pair of edge intersections. For each span of pixel locations, the corresponding set of active objects is used to determine (600) a value for each of the locations within the span.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: December 7, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Timothy Merrick Long, Kok Tjoan Lie, Christopher Fraser, Kevin Moore
  • Patent number: 6795048
    Abstract: The apparatus 20 for processing pixels of a digital image comprises an image processor (600, 700, 800) for processing the pixels, wherein the image processor (600, 700, 800) comprises a plurality of color output channels 1304. The apparatus further comprises a controller (300) for configuring the image processor (600, 700, 800) to operate in a first color processing mode or a second color processing mode. The image processor (600, 700, 800) during the first color processing mode, processes pixels each having one or more pixel color components and outputs therefrom one said pixel at a time by outputting said one or more pixel color components on corresponding color output channels (1304). The image processor (600, 700, 800) during the second color processing mode, processes pixels each having one pixel color component and outputs therefrom one or more pixels at a time by outputting corresponding one pixel color components on corresponding color output channels (1304).
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: September 21, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kok Tjoan Lie
  • Patent number: 6725299
    Abstract: Disclosed is method and apparatus (20) for improving the performance of a pipeline system in which a FIFO (24) is incorporated in the pipeline between an upstream processing module (22) and a downstream processing module (26), each of the modules (22, 26) having access to a common external memory (32), this being typical in many ASIC arrangements. The method commences with detecting when the FIFO (24) is substantially full and transferring commands from the upstream module (22) to the external memory (32). Commands received by the downstream module (26) from each of the FIFO (24) and the external memory (32) are interpreted to determine a source of following ones of the commands.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: April 20, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kok Tjoan Lie
  • Publication number: 20020175925
    Abstract: The apparatus 20 for processing pixels of a digital image comprises an image processor (600, 700, 800) for processing the pixels, wherein the image processor (600, 700, 800) comprises a plurality of color output channels 1304. The apparatus further comprises a controller (300) for configuring the image processor (600, 700, 800) to operate in a first color processing mode or a second color processing mode. The image processor (600, 700, 800) during the first color processing mode, processes pixels each having one or more pixel color components and outputs therefrom one said pixel at a time by outputting said one or more pixel color components on corresponding color output channels (1304). The image processor (600, 700, 800) during the second color processing mode, processes pixels each having one pixel color component and outputs therefrom one or more pixels at a time by outputting corresponding one pixel color components on corresponding color output channels (1304).
    Type: Application
    Filed: May 2, 2001
    Publication date: November 28, 2002
    Inventor: Kok Tjoan Lie
  • Publication number: 20010018734
    Abstract: Disclosed is method and apparatus (20) for improving the performance of a pipeline system in which a FIFO (24) is incorporated in the pipeline between an upstream processing module (22) and a downstream processing module (26), each of the modules (22, 26) having access to a common external memory (32), this being typical in many ASIC arrangements. The method commences with detecting when the FIFO (24) is substantially full and transferring commands from the upstream module (22) to the external memory (32). Commands received by the downstream module (26) from each of the FIFO (24) and the external memory (32) are interpreted to determine a source of following ones of the commands.
    Type: Application
    Filed: January 26, 2001
    Publication date: August 30, 2001
    Inventor: Kok Tjoan Lie