Patents by Inventor Kok-Yong Tan

Kok-Yong Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907059
    Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: February 20, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Publication number: 20230297464
    Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.
    Type: Application
    Filed: April 7, 2022
    Publication date: September 21, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 11609822
    Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes the following. When the memory storage device is powered-on, it is determined whether a power loss state of the memory storage device matches an unexpected power loss state according to a power-off instruction. Data is written into a plurality of physical programming units using a single-page programming mode and not using a multi-page programming mode when it is determined that the power loss state matches the unexpected power loss state.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 21, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Publication number: 20220342765
    Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes the following. When the memory storage device is powered-on, it is determined whether a power loss state of the memory storage device matches an unexpected power loss state according to a power-off instruction. Data is written into a plurality of physical programming units using a single-page programming mode and not using a multi-page programming mode when it is determined that the power loss state matches the unexpected power loss state.
    Type: Application
    Filed: June 3, 2021
    Publication date: October 27, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 11409472
    Abstract: A trim command processing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a trim command from a host system, where the trim command is configured to indicate data stored in at least one logical address among a plurality of logical addresses can be erased; calculating a first data volume of data required to be programmed when a data trim operation is performed according to the trim command; and determining whether to perform a first trim operation or a second trim operation according to the first data volume.
    Type: Grant
    Filed: March 28, 2021
    Date of Patent: August 9, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 11221946
    Abstract: A data arrangement method, a memory storage device and a memory control circuit unit are provided. The data arrangement method includes: receiving a command from a host, and the command includes a data range; calculating a data disarranged degree according to a logical estimated value of a plurality of logical block addresses of the data range and a physical estimated value of a plurality of physical erasing units mapped to the plurality of logical block addresses of the data range; and determining whether to perform a data arrangement operation according to the data disarranged degree and a threshold to move data in the plurality of physical erasing units according to the plurality of logical block addresses.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: January 11, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Publication number: 20210255950
    Abstract: A data arrangement method, a memory storage device and a memory control circuit unit are provided. The data arrangement method includes: receiving a command from a host, and the command includes a data range; calculating a data disarranged degree according to a logical estimated value of a plurality of logical block addresses of the data range and a physical estimated value of a plurality of physical erasing units mapped to the plurality of logical block addresses of the data range; and determining whether to perform a data arrangement operation according to the data disarranged degree and a threshold to move data in the plurality of physical erasing units according to the plurality of logical block addresses.
    Type: Application
    Filed: March 30, 2020
    Publication date: August 19, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 10884652
    Abstract: A trim command recording method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a write command from a host system; writing a data corresponding to the write command to a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units; and when receiving a trim command from the host system, writing a trim command record corresponding to the trim command into a second physical programming unit of the first physical erasing unit.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: January 5, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 10620874
    Abstract: A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first write command and writing data corresponding to the first write command into a first spare physical erasing unit; detecting an amount of second spare physical erasing units excluding the first spare physical erasing unit; determining whether the amount of the second spare physical erasing units is less than a threshold value; and performing a first procedure if the amount of the second spare physical erasing units is less than the threshold value. The first procedure includes: moving valid data in the physical erasing units into at least one third spare physical erasing unit; and adjusting the threshold value from a first threshold value to a second threshold value.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Horng-Sheng Yan, Kok-Yong Tan
  • Patent number: 10564862
    Abstract: A wear leveling method for a rewritable non-volatile memory module, a memory control circuit unit, and a memory storage apparatus are provided. The rewritable non-volatile memory module includes a plurality of physical erasing units. The method includes: recording an operation value of each of the physical erasing units; recording a usage situation value of each of the physical erasing units; and selecting a first physical erasing unit and a second physical erasing unit from the physical erasing units according to the operation values of the physical erasing units and the usage situation values of the physical erasing units and copying valid data stored in the first physical erasing unit to the second physical erasing unit.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: February 18, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Publication number: 20190324904
    Abstract: A trim command recording method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a write command from a host system; writing a data corresponding to the write command to a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units; and when receiving a trim command from the host system, writing a trim command record corresponding to the trim command into a second physical programming unit of the first physical erasing unit.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 24, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Publication number: 20190317673
    Abstract: A wear leveling method for a rewritable non-volatile memory module, a memory control circuit unit, and a memory storage apparatus are provided. The rewritable non-volatile memory module includes a plurality of physical erasing units. The method includes: recording an operation value of each of the physical erasing units; recording a usage situation value of each of the physical erasing units; and selecting a first physical erasing unit and a second physical erasing unit from the physical erasing units according to the operation values of the physical erasing units and the usage situation values of the physical erasing units and copying valid data stored in the first physical erasing unit to the second physical erasing unit.
    Type: Application
    Filed: May 25, 2018
    Publication date: October 17, 2019
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 10409525
    Abstract: A memory management method for a rewritable non-volatile memory module is provided. The method includes: selecting at least one first physical erasing unit from at least part of physical erasing units according to a first parameter. The method further includes: selecting a second physical erasing unit from the at least one first physical erasing unit according to a second parameter, wherein the second parameter is different from the first parameter; and copying at least part of data stored in the second physical erasing unit to a third physical erasing unit.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 10, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 10338854
    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: July 2, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Kok-Yong Tan, Horng-Sheng Yan
  • Patent number: 10191659
    Abstract: A data access method for a memory storage device is provided. The memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: receiving at least one operation command including at least one read command; and counting an amount of accumulative data of the at least one read command, and if the amount of accumulative data reaches a data threshold, writing the data in the buffer memory into the rewritable non-volatile memory module.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: January 29, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 10101914
    Abstract: A memory management method for a rewritable non-volatile memory module is provided. The memory management method includes receiving an adjust command from a host system, wherein the adjust command is configured to indicate that data stored in at least one logical unit of a plurality of logical units is invalid; updating a logical address status table according to the adjust command, wherein the logical address status table reflects a data status of the data stored in each of the logical units, wherein the data status includes a first state or a second state; and updating a physical address status table according to the logical address status table and the physical address status table if a predetermined condition is met, wherein the physical address status table reflects a data status of data stored in each of a plurality of physical programming units.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: October 16, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Kok-Yong Tan, Horng-Sheng Yan
  • Patent number: 9965400
    Abstract: A memory management method for a rewritable non-volatile memory module is provided. The memory management method includes using a first management mode to manage the rewritable non-volatile memory module after the rewritable non-volatile memory module is powered on; and using a second management mode to manage the rewritable non-volatile memory module if a shut down command is received from a host system, wherein the second management mode is different from the first management mode and the second management mode executes at least one mandatory processing procedure in background.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 8, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 9946478
    Abstract: A memory managing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: setting a read-disturb threshold for each of a plurality of physical erasing units; adjusting the read-disturb threshold of a first physical erasing unit according to state information of a rewritable non-volatile memory module; and performing a read-disturb prevention operation according to the read-disturb threshold of the first physical erasing unit.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: April 17, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 9875027
    Abstract: A data transmitting method for a memory storage device is provided. The method includes: detecting a temperature of the memory storage device; and determining whether the temperature of the memory storage device is greater than a temperature threshold. If the temperature is greater than the temperature threshold, first data is written into a rewritable non-volatile memory module within a first delay time according to a delay count corresponding to a unit temperature.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 23, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan
  • Patent number: 9772797
    Abstract: A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The method includes allocating a first zone and a second zone in the buffer memory for temporarily storing a plurality of logical address-physical address mapping tables and performing a restore operation on the first zone. The method also includes receiving a write command, wherein a logical address-physical address table to which a logical address indicated by the write command belongs has been temporarily stored in the first zone. The method further includes copying the logical address-physical address table into the second zone, and updating the logical address-physical address table in the second zone.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: September 26, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Kok-Yong Tan