Patents by Inventor Koki Noguchi
Koki Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8090398Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: GrantFiled: April 30, 2008Date of Patent: January 3, 2012Assignee: Renesas Electronics CorporationInventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
-
Patent number: 7558944Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: GrantFiled: March 7, 2008Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
-
Publication number: 20080294873Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: ApplicationFiled: March 7, 2008Publication date: November 27, 2008Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
-
Publication number: 20080207158Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: April 30, 2008Publication date: August 28, 2008Inventors: Tetsuya NAKAGAWA, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
-
Patent number: 7363466Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: GrantFiled: February 14, 2006Date of Patent: April 22, 2008Assignee: Renesas Technology Corp.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
-
Patent number: 7138722Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: GrantFiled: February 15, 2005Date of Patent: November 21, 2006Assignee: Renesas Technology Corp.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
-
Publication number: 20060224859Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: ApplicationFiled: February 14, 2006Publication date: October 5, 2006Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
-
Patent number: 7069423Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: GrantFiled: July 22, 2002Date of Patent: June 27, 2006Assignee: Hitachi, Ltd.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
-
Publication number: 20060085563Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: November 30, 2005Publication date: April 20, 2006Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
-
Patent number: 6993597Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: GrantFiled: August 13, 2003Date of Patent: January 31, 2006Assignee: Renesas Technology Corp.Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
-
Publication number: 20050146008Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: ApplicationFiled: February 15, 2005Publication date: July 7, 2005Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
-
Patent number: 6900074Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: GrantFiled: April 25, 2003Date of Patent: May 31, 2005Assignee: Renesas Technology Corp.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
-
Patent number: 6889240Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.Type: GrantFiled: October 29, 2003Date of Patent: May 3, 2005Assignee: Renesas Technology Corp.Inventors: Atsushi Kiuchi, Yuji Hatano, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
-
Patent number: 6810454Abstract: An information processing apparatus includes a master module serving as a transfer source, a slave module serving as a transfer destination, a bus of a source clock synchronous system, and a means for transferring a signal based upon a protocol of an acknowledge type from the slave module to the master module via the bus of the source clock synchronous system. In the information processor, the signals of the acknowledge type are also transferred in the source clock synchronous system by using a source clock signal dedicated to signals of the acknowledge type. Therefore, it is prevented that the master side fails in acquiring signals of the acknowledge type from the slave side, and the reliability of the source clock synchronous bus and the data efficiency can be improved.Type: GrantFiled: January 8, 2003Date of Patent: October 26, 2004Assignee: Renesas Technology Corp.Inventors: Nobukazu Kondo, Ikuya Kawasaki, Koki Noguchi
-
Publication number: 20040083250Abstract: In microcomputers and digital signal processorsin which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chipthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing.Type: ApplicationFiled: October 29, 2003Publication date: April 29, 2004Applicant: Hitachi, Ltd.Inventors: Atsushi Kiuchi, Yuji Hatano, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
-
Method and apparatus for converting non-burst write cycles to burst write cycles across a bus bridge
Patent number: 6728813Abstract: For improving data efficiency of a bus in a system using address/data multiplex bus, in a processor for information processing equipment, there are provided buffers which store plural sets of write addresses and data for a system bus, a comparator for deciding whether write addresses in succession forming a continuous write address exist in the write addresses stored in the buffers, and apparatus for converting access corresponding to writing operations for the continuous write addresses into a fixed length burst transfer protocol which can be transferred with a series of continuing data cycles following one address cycle, when the comparator 27 decides that write addresses in succession exist.Type: GrantFiled: February 16, 1999Date of Patent: April 27, 2004Assignee: Renesas Technology Corp.Inventors: Nobukazu Kondo, Tomohisa Kohiyama, Koki Noguchi -
Patent number: 6708304Abstract: A semiconductor device including a port circuit (301) connected to an internal circuit, external terminals to which the port circuit is connected and a boundary scanning circuit (180, 18), the boundary scanning circuit being the one that makes access to the external terminals through the test access terminals. The test access terminals are also used as predetermined external terminals among the external terminals. Selection means (301, 303 to 307) are provided for selectively determining whether the multi-use terminals (P1 to P5) be connected to the port circuit or to the boundary scanning circuit, and for selecting, as an initial state, the state where the multi-use terminals are connected to the boundary scanning circuit in response to the power-on reset. Since the test access terminals need not be dedicated, the boundary scanning function can be furnished while guaranteeing pin compatibility of external terminals.Type: GrantFiled: September 15, 2000Date of Patent: March 16, 2004Assignee: Renesas Technology CorporationInventors: Akifumi Tsukimori, Ikuya Kawasaki, Shinichi Yoshioka, Koki Noguchi
-
Publication number: 20040049606Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.Type: ApplicationFiled: August 13, 2003Publication date: March 11, 2004Inventors: Tetsuya Nakagawa, Yuji Hatano, Yasuhiro Sagesaka, Toru Baji, Koki Noguchi
-
Patent number: 6668266Abstract: In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.Type: GrantFiled: October 11, 2001Date of Patent: December 23, 2003Assignee: Hitachi, Ltd.Inventors: Atsushi Kiuchi, Yuji Hatano, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
-
Patent number: 6665807Abstract: A circuit includes a transmission function of transmitting data together with a source clock synchronized to the data to another module, a reception circuit for receiving the data outputted by the module and a source clock synchronized to the data, and a synchronization circuit for connecting the circuit having a transmission function to the reception circuit are formed on a single-chip integrated circuit. Even if the module connected to the bus is changed, i.e., even if the operation clock frequency of the module of the other party is changed, other modules can be used as they are without making any change. The cost needed at the time of system construction can thus be reduced. Furthermore, as for the aspect of performance, only one synchronization circuit is needed. The increase of latency caused by synchronization can also be suppressed to the minimum.Type: GrantFiled: September 3, 1999Date of Patent: December 16, 2003Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Koki Noguchi, Ikuya Kawasaki