Abstract: Submicron contact holes in semiconductor bodies are metalized in a single operation. A titanium-rich layer is first deposited, which is followed by a low-resistance TiSi.sub.2 layer. The two layers are thus deposited in one contiguous CVD process inside a single CVD chamber.

Abstract: In the method, the totality of the gases is conducted through an absorption cell. A reference cell contains a reference gas. The cells are optically transirradiated and a signal representing a quantity for the mass flow to be identified is generated in a detector which picks up the optical radiation emerging from the cells.

Abstract: Methods and apparatus for producing conductive layers or structures for VLSI circuits. In a method for producing conductive layers or structures for VLSI circuits, at least two method stages are implemented in direct succession in different chambers of a high-vacuum system without interrupting the high-vacuum conditions for the semiconductor substrate. Avoiding exposure to air between the method stages produces noticeably improved layer properties and enables particularly simple and reliable multi-stage methods for producing conductive layers that promote a multi-layer wiring on the semiconductor substrate. An apparatus for implementing the method has a plurality of high-vacuum process chambers, at least one high-vacuum distributor chamber connecting the process chambers and of at least two high-vacuum supply chambers for semiconductor substrates.

Abstract: In the ozone-activated deposition of insulating layers, different growth rates can be achieved on differently constituted surfaces. When the surfaces of the structured silicon substrates lying at different levels are differently constituted or, respectively, are intentionally varied such that the SiO.sub.2 insulating layer grows more slowly on the higher surfaces than on the more deeply disposed surfaces and when deposition is carried out until the surfaces of the rapidly growing and slowly growing layer regions form a step-free, planar level, a local and global planarization is achieved.

Abstract: The method for monitoring an end point of an etching process of electrically insulating layers effected by ions, radicals and/or neutral particles in a plasma is accomplished with the assistance of a reference substrate having a defined specimen geometry which is situated on a mobile substrate holder with the layers to be etched. The electrical resistance is measured and a voltage drop of a known constant current is impressed at known time intervals onto an electrically conductive layer lying under the layer to be etched. Measurement of the voltage drop is continued until an injection current is additionally injected into the conductive layer by the plasma to change the voltage drop. Test data is transmitted in non-contacting fashion by pulse code modulated electromagnetic radiation using a telemetry system so that the movable substrate is an independent unit.

Abstract: A method for controlling and supervising etching processes effected by ions, radicals, and/or neutral particles activated in a plasma includes identifying the etching rate and the final point of material erosion by the use of a reference substrate having a defined specimen geometry and situated on a moveable substrate holder in a recipient compartment or etching chamber. The electrical resistance of the specimen, which is dependent on the layer thickness of an electrically conductive layer, is measured and the measured data is transmitted in non-contacting fashion by electromagnetic radiation using pulse code modulation methods. A telemetric metrology system is used which is mounted on the moveable substrate holder as an independent unit. A process control computer supervises and, if need be, controls the etching parameters in the plasma.

Abstract: Cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories (SRAMs) with buried contacts to the n.sup.+ and p.sup.+ regions in the substrate are obtained in accordance with known method steps and with a high packing density. A gate level thereof formed of a polycide double layer is used as an additional wiring level for the cross-coupling. The formation of the gate level occurs after the opening of regions for the buried contacts. A doping occurs simultaneously with the generation of source/drain regions of the n-channel and p-channel transistors by masked ion implantation and a subsequent high-temperature treatment. Accordingly, simple, mask-non-intensive method steps result which are especially useful in the manufacture of 6-transistor SRAMs.

Abstract: An integrated semiconductor circuit consisting of a silicon substrate having an impurity doped circuit therein, and a layer of silicon dioxide formed on the substrate and having a contact hole therein overlying the circuit. An outer contact interconnect level composed of aluminum or an aluminum alloy provides electrical contact to the circuit. A tantalum disilicide diffusion barrier layer is disposed between the circuit and the interconnect level, with a layer of substantially pure tantalum both above and below the tantalum disilicide diffusion barrier layer.

Abstract: Chemical reactions between a tantalum or tantalum silicide metallization layer and an underlying thin gate oxide are avoided by the interposition of an intermediate layer of oxygen-doped tantalum or tantalum silicide whose thickness amounts to about 1/20 to 1/5 of the layer thickness of the entire gate metallization. The metallization layer is produced by high-frequency sputtering in which oxygen is added at the beginning of the process and argon is used as a sputtering gas. Low specific resistance values are accomplished by means of this gate metallization.

Abstract: A method for manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon. The polycystalline silicon is deposited in undoped fashion before the metal silicide and the doping of the silicon is obtained through the production of the source/drain-zones through ion implantation and a subsequent high temperature step. The method permits the problem-free manufacture of polycide-gates with n.sup.+ - and p.sup.+ -polysilicon on a chip without increased technological expense. Planarization is facilitated through the thin gate layers. The method is used in the manufacture of highly integrated CMOS-circuits.

Abstract: A method for the deposition of a silicide layer of a high melting metal onto a substrate of silicon or silicon dioxide wherein reaction gases consisting of a decomposable silicon-containing hydrogen compound, or a halogenated silane and a metal halide are pyrolytically decomposed in a reaction zone to form a reaction mixture from which a metal silicide is deposited on the substrate at reduced pressures. During the decomposition of the gases and deposition of the metal silicide, the gas pressure in the reaction zone is maintained between 1.3.times.10.sup.-3 to 5.times.10.sup.-2 mbar. This type of pressure is most conveniently maintained by means of a turbomolecular pump.

Abstract: A method for monitoring and regulating composition and layer thickness of metallically conductive alloy layers during their manufacture by means of electrical resistance measurement. Individual alloy components are cyclically applied in coats in chronological succession. By comparison of measured actual values of the layer resistance R.sub.G after the application of each and every individual coating to rated values determined before the layer manufacture, the coating rates of the corresponding alloy component sources are controlled. The method serves for the reproducible manufacture of thin metal layers in semiconductor technology and allows the control of composition and layer thickness even during manufacture of said layers.

Abstract: A method of measuring the electrical resistance of thin metallic films manufactured under the influence of a plasma. The measurement proceeds by means of a direct current resistance measurement according to the principle of a two point or four point measuring method. The electrical resistance is determined either in the case of at least one measuring or test current, and the voltage connected to the measuring contacts is measured when no measuring or test current is sent through the film, or the electrical resistance is determined in the case of at least two different measuring or test currents of known magnitudes. The measuring methods are applied in the case of manufacture of metallic layers in semiconductor technology, in particular also for the measurement of the ion current injected in the film by the plasma as well as for the determination of variations in the coating rate.

Abstract: A system for measuring electrical resistance and temperature during the manufacture of thin, conductive films deposited on substrates by means of evaporation or sputter-deposition. A deposition unit with an evacuatable load lock chamber and a rotating substrate holder are employed as the deposition system. The specific electrical resistance of the film is measured according to the principle of the two-point or four-point measuring methods at a reference substrate with specific sample geometry and with low-resistance contacts. The substrate temperature is measured by means of resistance thermometers. With the invention, the transmission of the measured data occurs contact-free by means of electro-magnetic radiation, preferably by means of a telemetric pulse code modulation method.

Abstract: A method for the manufacture of integrated MOS-field effect transistor circuits in silicon gate technology and wherein diffusion source and drain zones are coated with a high melting point silicide as low-impedance printed conductors. The diffusion zones and polysilicon gates are made low-impedance through selective deposition of the metal silicide onto surfaces thereof. The selective deposition, which proceeds by use of a reaction gas eliminating hydrogen halide, simplifies the process sequence and is fully compatible with conventional silicon gate processes. Because of the high temperature stability, preferably tantalum silicide is employed. The invention is useful in the manufacture of MOS-circuits in VLSI-technology.

Abstract: Structured layers composed of high melting point metal silicides, such as tantalum silicide, are selectively deposited on substrates having at least some silicon and some non-silicon regions, such as are used in thin-film and semiconductor technology, by thermal decomposition of gaseous silicon and halogen compounds containing a high melting point metal in a reaction gas and depositing the metal silicide onto the silicon regions of the substrates while providing a gaseous hydrogen halide, such as hydrogen chloride, to the reaction gas and adjusting the substrate deposition temperature and the composition of the reaction gas to values at which a silicide nucleation in substrate regions, other than silicon regions, is suppressed during deposition of the metal silicide from the gaseous phase due to the presence of the hydrogen halide. The invention is useful for producing contact track levels in VLSI circuits.

Abstract: Thin film electrical resistors comprised of a substantially homogeneous amorphous chromium-silicon-oxygen alloy having an empirical formula of Cr.sub.x Si.sub.y O.sub.z wherein X is a number in the range of about 0.3 to 0.39, y is a number in the range of about 0.4 to 0.52 and x is a number in the range of about 0.1 to 0.30, with the proviso that some of x, y and z is equal to 1. Such resistors exhibit a relatively high ohmic resistance in the range of about 2,000 to 16,000 .mu..OMEGA..multidot.cm.

Abstract: Monocrystalline metal layers having a low specific electrical resistance (.rho.<15.mu..OMEGA. cm) are produced by depositing a layer of a select metal or alloy in its polycrystalline state onto a substrate useful in semiconductor and thin film technologies, such as composed of glass, ceramic or silicon; substantially simultaneously with the deposition or thereafter, implanting ions which are inert relative to the metal or alloy so as to generate crystal lattice disruptions in the deposited layer and thereafter heating the so-coated substrate so as to convert the polycrystalline layer into its monocrystalline state. The principles of the invention are particularly applicable for the production of lead structures in micro-electronics.

Abstract: Reproducible manufacture of metallic layers for semiconductor and thin film technology is attained by dynamic control of the layering process whereby the specific electrical resistance, .rho., is determined as a function of layer thickness, d, and layering parameters are regulated by a process-control computer. With this process, factors effecting the growth of a layer with respect to its structure, texture and composition are identified and calculated as measured values of .rho. and d, by the process-control computer and corrections for individual layering parameters are calculated via a suitable control program. In this manner, the nucleation of a layer and its growth is influenced in such a manner that the layer exhibits the desired electrical, structural and texture properties in its final state.

Abstract: Disclosed herein is a process for the chemical deposition of a material layer on the inside of cavities of a work piece by conducting a gas stream in a substantially laminar flow along a heated work piece wherein deposition occurs from the gaseous phase, at a pressure of less than 10.sup.4 Pascal (N/m.sup.2).