Patents by Inventor Konrad K. Lai

Konrad K. Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8782382
    Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Peter Lachner, Laura A. Knauth, Konrad K. Lai
  • Publication number: 20140059333
    Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.
    Type: Application
    Filed: February 2, 2012
    Publication date: February 27, 2014
    Inventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
  • Publication number: 20130205119
    Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
    Type: Application
    Filed: June 29, 2012
    Publication date: August 8, 2013
    Inventors: Ravi Rajwar, Bret L. Toll, Konrad K. Lai, Matthew C. Merten, Martin G. Dixon
  • Patent number: 8479053
    Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: July 2, 2013
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Peter Lachner, Laura A. Knauth, Konrad K. Lai
  • Patent number: 8301849
    Abstract: Methods, systems, and apparatuses to provide an XABORT in a transactional memory access system are described. In one embodiment, the stored value is a context value indicating the context in which a transactional memory execution was aborted. A fallback handler may use the context value to perform a series of operations particular to the context in which the abort occurred.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: October 30, 2012
    Assignee: Intel Corporation
    Inventors: Ravi Rajwar, Martin G. Dixon, Konrad K. Lai
  • Publication number: 20120227045
    Abstract: An apparatus, method, and system are described herein for providing programmable control of performance/event counters. An event counter is programmable to track different events, as well as to be checkpointed when speculative code regions are encountered. So when a speculative code region is aborted, the event counter is able to be restored to it pre-speculation value. Moreover, the difference between a cumulative event count of committed and uncommitted execution and the committed execution, represents an event count/contribution for uncommitted execution. From information on the uncommitted execution, hardware/software may be tuned to enhance future execution to avoid wasted execution cycles.
    Type: Application
    Filed: February 2, 2012
    Publication date: September 6, 2012
    Inventors: Laura A. Knauth, Ravi Rajwar, Peggy J. Irelan, Martin G. Dixon, Konrad K. Lai
  • Publication number: 20120030518
    Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.
    Type: Application
    Filed: July 28, 2010
    Publication date: February 2, 2012
    Inventors: Ravi Rajwar, Peter Lachner, Laura A. Knauth, Konrad K. Lai
  • Publication number: 20110197182
    Abstract: Methods and apparatus relating to debugging parallel software using speculatively executed code sequences in a multiple core environment are described. In an embodiment, occurrence of a speculative code debug event is detected and a speculative code execution debug module is executed in response to occurrence of the event. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 24, 2010
    Publication date: August 11, 2011
    Inventors: Peter Lachner, Konrad K. Lai, Ravi Rajwar
  • Publication number: 20110161639
    Abstract: A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the event counter to the stored event count after the event counter has counted additional events. Other methods are also disclosed. Apparatus, systems, and machine-readable medium having software are also disclosed.
    Type: Application
    Filed: December 26, 2009
    Publication date: June 30, 2011
    Inventors: Laura A. Knauth, Ravi Rajwar, Konrad K. Lai, Martin G. Dixon, Peggy Irelan
  • Publication number: 20110153960
    Abstract: Methods, systems, and apparatuses to provide an XABORT in a transactional memory access system are described. In one embodiment, the stored value is a context value indicating the context in which a transactional memory execution was aborted. A fallback handler may use the context value to perform a series of operations particular to the context in which the abort occurred.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Ravi Rajwar, Martin G. Dixon, Konrad K. Lai
  • Publication number: 20110153992
    Abstract: Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass code to execute in a managed runtime in response to receiving the object lock request. The example method also includes identifying a type of instruction set architecture (ISA) associated with the processor, invoking a checkpoint instruction for the processor based on the identified ISA, suspending the object lock code from executing and executing target code when the object is uncontended, and allowing the object lock code to execute when the object is contended.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Suresh Srinivas, Stephen H. Dohrmann, Mingqiu Sun, Uma Srinivasan, Ravi Rajwar, Konrad K. Lai
  • Patent number: 6397291
    Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: May 28, 2002
    Assignee: Intel Corporation
    Inventors: Randy M. Bonella, Peter D. MacWilliams, Konrad K. Lai
  • Publication number: 20010011317
    Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.
    Type: Application
    Filed: December 5, 2000
    Publication date: August 2, 2001
    Inventors: Randy M. Bonella, Peter D. MacWilliams, Konrad K. Lai
  • Patent number: 6192459
    Abstract: A data retrieval system receives a data address identifying data to be retrieved. A portion of the received data address is communicated to a data storage device during a first clock cycle. The system determines a second address portion based on the received data address. The second address portion is communicated to the data storage device during a second clock cycle. Data is then retrieved from the data storage device based on the address portions communicated to the data storage device. The portion of the received data address communicated to the data storage device during the first clock cycle is a set address and the second address portion communicated to the data storage device during the second clock cycle is a way address. A read cycle can be initiated after communicating a portion of the received data address to the data storage device during the first clock cycle.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: February 20, 2001
    Assignee: Intel Corporation
    Inventors: Randy M. Bonella, Peter D. MacWilliams, Konrad K. Lai
  • Patent number: 6006299
    Abstract: In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: December 21, 1999
    Assignee: Intel Corporation
    Inventors: Wen-Hann Wang, Konrad K. Lai, Gurbir Singh, Mandar S. Joshi, Nitin V. Sarangdhar, Matthew A. Fisch
  • Patent number: 5966722
    Abstract: A method and apparatus for controlling an integrated circuit (IC) die with another IC die. The present invention uses a processor to control the operation of a cache memory die. In this manner, the cache memory is directed by the processor as to the operations to be performed, such as writing to the cache memory. A dedicated bus is coupled between the two dice. This dedicated bus is used to send control and other signals between the two dice.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: October 12, 1999
    Assignee: Intel Corporation
    Inventors: Gurbir Singh, Konrad K. Lai
  • Patent number: 5937171
    Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
    Type: Grant
    Filed: June 26, 1996
    Date of Patent: August 10, 1999
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Peter D. MacWilliams
  • Patent number: 5903908
    Abstract: A method and apparatus for controlling multiple cache memories with a single cache controller. The present invention uses a processor to control the operation of its on-chip level one (L1) cache memory and a level two (L2) cache memory. In this manner, the processor is able to send operations to be performed to the L2 cache memory, such as writing state and/or cache line status to the L2 cache memory. A dedicated bus is coupled between dice. This dedicated bus is used to send control and other signals between the processor and the L2 cache memory.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: May 11, 1999
    Assignee: Intel Corporation
    Inventors: Gurbir Singh, Konrad K. Lai, Michael W. Rodehamel
  • Patent number: 5903738
    Abstract: A method and apparatus of performing bus transactions on the external bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: May 11, 1999
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh
  • Patent number: RE38388
    Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: January 13, 2004
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Peter D. MacWilliams, Stephen S. Pawlowski, Michael W. Rhodehamel