Patents by Inventor Kooi Chi Ooi

Kooi Chi Ooi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200126928
    Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 ?m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.
    Type: Application
    Filed: June 25, 2019
    Publication date: April 23, 2020
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong, Kooi Chi Ooi, Min Suet Lim
  • Patent number: 10606316
    Abstract: A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Kooi Chi Ooi, Bok Eng Cheah, Eng Huat Goh
  • Publication number: 20200083194
    Abstract: Discussed generally herein are devices that can include multiple stacked dice electrically coupled to dice electrically coupled to a peripheral sidewall of the stacked dice and/or a dice stack electrically coupled to a passive die. In one or more embodiments a device can include a dice stack comprising at least two dice including a first die and a second die, the first die electrically connected to and on a second die, a first side pad on, or at least partially in, a first sidewall of the dice stack, a third die electrically connected to the first die at a first surface of the third die and through the first side pad, and a fourth die electrically connected to the third die at a second surface of the first die, the second side opposite the first side.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 12, 2020
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Ping Ping Ooi
  • Patent number: 10580761
    Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Boon Ping Koh, Kooi Chi Ooi
  • Publication number: 20200027813
    Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a base package, an ancillary package, and an electrically isolated metal layer. The base package may include a base die. The ancillary package may include an ancillary component. The ancillary package may be located on top of the base package. The electrically isolated metal layer may be located at least partially within a layer of the base package such that a portion of the electrically isolated metal layer contacts at least one surface of the base die and is located in between the base die and the ancillary component.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 23, 2020
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Ping Ping Ooi
  • Publication number: 20190355681
    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.
    Type: Application
    Filed: December 19, 2017
    Publication date: November 21, 2019
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Ping Ping Ooi, Kooi Chi Ooi
  • Patent number: 10403604
    Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Ping Ping Ooi, Kooi Chi Ooi, Shanggar Periaman
  • Patent number: 10394280
    Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the user's skin in the portion of the user's body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the user's body, the second electrode is arranged to not contact the user's skin in the portion of the user's body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 27, 2019
    Assignee: INTEL CORPORATION
    Inventors: Thorsten Meyer, Dirk Plenkers, Hans-Joachim Barth, Bernd Waidhas, Yen Hsiang Chew, Kooi Chi Ooi, Howe Yin Loo
  • Patent number: 10396038
    Abstract: A flexible packaging architecture is described that is suitable for curved package shapes. In one example a package has a first die, a first mold compound layer over the first die, a wiring layer over the first mold compound layer, a second die over the wiring layer and electrically coupled to the wiring layer, and a second mold compound layer over the second die.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Shanggar Periaman, Michael Skinner, Yen Hsiang Chew, Kheng Tat Mar, Ridza Effendi Abd Razak, Kooi Chi Ooi
  • Publication number: 20190259704
    Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 22, 2019
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Kooi Chi Ooi, Paik Wen Ong
  • Patent number: 10354957
    Abstract: An electrical interconnect for an electronic package. The electrical interconnect includes a first dielectric layer; a second dielectric layer; a signal conductor positioned between the first dielectric layer and the second dielectric layer; and a conductive reference layer mounted on the first dielectric layer, and wherein the conductive reference layer does not cover the signal conductor. The conductive reference layer may be a first conductive reference layer and the electrical interconnect further comprises a second conductive reference layer mounted on the second dielectric layer. The second conductive reference layer does not cover the signal conductor. In addition, the signal conductor may be a first signal conductor and the electrical interconnect may further include a second signal conductor between the first dielectric layer and the second dielectric layer. The first and second signal conductors may form a differential pair of conductors.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Stephen Harvey Hall, Khang Choong Yong, Kooi Chi Ooi, Eric C Gantner
  • Publication number: 20190181126
    Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.
    Type: Application
    Filed: June 26, 2018
    Publication date: June 13, 2019
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Boon Ping Koh, Kooi Chi Ooi
  • Publication number: 20190109122
    Abstract: A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.
    Type: Application
    Filed: December 18, 2017
    Publication date: April 11, 2019
    Inventors: Jenny Shio Yin Ong, Bok Eng Cheah, Jackson Chung Peng Kong, Seok Ling Lim, Kooi Chi Ooi
  • Publication number: 20190103359
    Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.
    Type: Application
    Filed: December 18, 2017
    Publication date: April 4, 2019
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Kooi Chi Ooi, Paik Wen Ong
  • Publication number: 20190050715
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve data training of a machine learning model using a field-programmable gate array (FPGA). An example system includes one or more computation modules, each of the one or more computation modules associated with a corresponding user, the one or more computation modules training first neural networks using data associated with the corresponding users, and FPGA to obtain a first set of parameters from each of the one or more computation modules, the first set of parameters associated with the first neural networks, configure a second neural network based on the first set of parameters, execute the second neural network to generate a second set of parameters, and transmit the second set of parameters to the first neural networks to update the first neural networks.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 14, 2019
    Inventors: Kooi Chi Ooi, Min Suet Lim, Denica Larsen, Lady Nataly Pinilla Pico, Divya Vijayaraghavan
  • Publication number: 20190047559
    Abstract: Apparatuses and methods for evaluating the risk factors of a proposed vehicle maneuver using remote data are disclosed. In embodiments, a computer-assisted/autonomous driving vehicle communicates with one or more remote data sources to obtain remote sensor data, and process such remote sensor data to determine the risk of a proposed vehicle maneuver. A remote data source may be authenticated and validated, such as by correlation with other remote data sources and/or local sensor data. Correlation may include performing object recognition upon the remote data sources and local sensor data. Risk evaluation is performed on the validated data, and the results of the risk evaluation presented to a vehicle operator or to an autonomous vehicle navigation system.
    Type: Application
    Filed: September 24, 2018
    Publication date: February 14, 2019
    Inventors: Naissa CONDE, Casey BARON, Shekoufeh QAWAMI, Kooi Chi OOI, Mengjie YU
  • Publication number: 20190050265
    Abstract: Methods, apparatus, systems, and articles of manufacture for allocating a workload to an accelerator using machine learning are disclosed. An example apparatus includes a workload attribute determiner to identify a first attribute of a first workload and a second attribute of a second workload. An accelerator selection processor causes at least a portion of the first workload to be executed by at least two accelerators, accesses respective performance metrics corresponding to execution of the first workload by the at least two accelerators, and selects a first accelerator of the at least two accelerators based on the performance metrics. A neural network trainer trains a machine learning model based on an association between the first accelerator and the first attribute of the first workload. A neural network processor processes, using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 14, 2019
    Inventors: Divya Vijayaraghavan, Denica Larsen, Kooi Chi Ooi, Lady Nataly Pinilla Pico, Min Suet Lim
  • Publication number: 20190049969
    Abstract: Apparatuses, methods and storage medium associated with computer-assisted or autonomous vehicle incident management, are disclosed herein. In some embodiments, a vehicle incident management system includes a main system controller to determine whether a vehicle hosting the apparatus is involved in a vehicle incident; if so, whether another vehicle is involved; and if so, whether the other vehicle is equipped to exchange incident information; and an inter-vehicle communication subsystem to exchange incident information with the other vehicle, on determination that the vehicle is involved in a vehicle incident involving the other vehicle, and the other vehicle is equipped to exchange incident information. Other embodiments are also described and claimed.
    Type: Application
    Filed: August 30, 2018
    Publication date: February 14, 2019
    Inventors: Shekoufeh Qawami, Casey Baron, Kooi Chi Ooi, Naissa Conde, Mengjie Yu
  • Publication number: 20190013301
    Abstract: Embodiments herein may include apparatuses, systems, and processes related to stacked dies that include recesses into which passive components, such as decoupling capacitors, may be included. Embodiments may include a first die with a first side and a second side opposite the first side, a second die with a first side coupled to the second side of the first die, a recess in the first side of the second die, wherein a portion of a passive component is located within the recess of the first side of the second die, and wherein the passive component is coupled with the first die, the second die, or both. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 1, 2018
    Publication date: January 10, 2019
    Inventors: Bok Eng CHEAH, Jackson Chung Peng KONG, Kooi Chi OOI
  • Publication number: 20180348823
    Abstract: A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.
    Type: Application
    Filed: December 10, 2015
    Publication date: December 6, 2018
    Inventors: Jackson Chung Peng KONG, Kooi Chi OOI, Bok Eng CHEAH, Eng Huat GOH