Patents by Inventor Kooji Serizawa

Kooji Serizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6188546
    Abstract: The magnetic head assembly including a magnetic head having a terminal composed of a conductive film and a supporting spring. The supporting spring has interconnecting patterns (lines) on the top thereof and a projective electrode. The terminal of the magnetic head is electrically connected to the projective electrode of the supporting spring by a solderless, direct contact connection. The magnetic head is fixed to the supporting spring by using a non-electrical bonding agent. This structure makes it possible to stabilize the position of the magnetic head assembly and the relative speed variation between the magnetic head element and the magnetic disk, thereby enhancing the reliability of the magnetic disk apparatus.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: February 13, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yasuyuki Nakajima, Keii Ueno, Michio Takahashi, Masayasu Fujisawa, Katsuya Fukasawa, Issei Takemoto, Kooji Serizawa, Kazushige Hashimoto, Shigeo Nakamura, Yukimori Umakoshi, Mikio Tokuyama
  • Patent number: 5440171
    Abstract: In a tape carrier type semiconductor device with reinforcement wherein tape carrier type semiconductor modules are mounted in holes or depressions enclosed by a frame, and at least one flexible circuit is stacked additionally as required, and the semiconductor modules are electrically connected to electrodes formed on the frame, by mounting chip parts such as capacitors on the frame and/or flexible circuit, the mounting area of the semiconductor device can be reduced and the performance can be hyperfunctioned. By stacking a plurality of such semiconductor devices with reinforcement, much more satisfactory effects can be obtained.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: August 8, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Miyano, Kooji Serizawa, Suguru Sakaguchi, Toshiharu Ishida
  • Patent number: 5421081
    Abstract: A method for producing an electronic part mounting structure in which electronic parts such as IC packages are electrically connected to the surface of a printed circuit board utilizes a low-melting point metal. More particularly, the method provides an electronic part mounting structure capable of sufficiently and assuredly supplying solder to a portion between the terminal of a printed circuit board and the leads of an electric part while maintaining a predetermined thickness required to connect the printed circuit board and the electronic part to each other. By arranging the structure such that a gap, in which a solder layer having a predetermined thickness can be formed between the terminal of the printed circuit board and the lead of the electronic part to be connected to the terminal, is formed, the solder required to solder-connect the two elements can be sufficiently and assuredly supplied to the gap. Therefore, a reliable solder connection can be established.
    Type: Grant
    Filed: May 13, 1993
    Date of Patent: June 6, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Suguru Sakaguchi, Toshiharu Ishida, Kooji Serizawa, Hiroyuki Tanaka, Ichiro Miyano, Hiroshi Nakamura
  • Patent number: 5219765
    Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device without waste by incorporating predetermined functions into a wafer in a wafer completion process, aging the wafer in a wafer aging process, distinguishing between non-defective and defective chips in a probe inspection process, separating chips in the wafer one by one in a dicing process, sorting out the chips into non-defective and defective chips in a selection process, then analyzing failure information and feeding back the result of the analysis to the wafer completion process in a feedback process, thereby quickly analyzing and repairing a failure process on reliability in the wafer completion process.
    Type: Grant
    Filed: July 6, 1990
    Date of Patent: June 15, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toru Yoshida, Suguru Sakaguchi, Aizo Kaneda, Kooji Serizawa, Munehisa Kishimoto, Masaaki Mutoh, Kunio Matsumoto, Isao Ohomori, Shingo Yorisaki