Abstract: A receiver of a system for transmitting data symbols at a given baud-rate comprises a symbol detector (7) operating at the baud-rate 1/T and means (6) for optimally conditioning received data symbols for this symbol detection. From the received conditioned data signal [s(k)], a phase error signal [E(K-1).c(K)] is derived that is representative of a phase difference between a locally generated baud-rate clock signal and a baud-rate clock signal inherent to the received data symbols, and the receiver comprises means (11, 12) for the reduction of this phase difference step-by-step in response to the phase error signal [e(k-1).c(k)]. This receiver further includes an accumulator (44) for determining the mean value [u(k)] of the phase error signal over a predetermined number (M) of symbol intervals and a detector (45) for establishing whether this means value [u(k)] is situated in a zone whose boundaries [.+-..sub.V r(k)/N] are determined by a given fraction (1/N, N>1) of the level [V.sub.

Abstract: An adaptive time-discrete filter having an impulse response h(i) with i=0,1,2, . . . for forming a cancelling signal from synchronous data symbols (for example to cancel echoes or lagging intersymbol interference) comprises a transversal filter section (12) having adjustable coefficients C.sub.i with i=0,1,2, . . . , N-1 for realizing the first N values h(i) of the impulse response as well as a recursive filter section (12') for realizing the values h(i) with i=N,N+1, . . . . The recursive filter section (12') receives the input signal delayed over N-1 discrete time intervals from the adaptive filter as an input signal x(n) and forms an output signal y(n) according to the relationship:y(n)=C.sub.B [C.sub.A .times.(n-1)+y(n-1)]where C.sub.A is equal to the last adjustable coefficient C.sub.N-1 of the transversal filter section (12) and C.sub.B is a predetermined fixed coefficient.

Abstract: A transceiver arrangement for full-duplex data transmission over a two-wire circuit (6) comprises a transmitter part (1-4), a receiver part (7, 8, 11-15), a hybrid junction (5) to interconnect the transmitter and receiver parts and the two-wire circuit (6), and an echo canceller 9 whose input is connected to the transmitter part and whose output is connected to the receiver part, the arrangement further comprising switching means (S.sub.1) enabled in a test mode for disconnecting the receiver part (7, 8, 11-15) from the two-wire circuit (6). With a single test the proper functioning of the transmitter and receiver parts of the arrangement as well as that of the echo canceller (9) can be checked, because the arrangement also comprises switching means (S.sub.

Abstract: A system for transmitting a data signal (a.sub.k) at a given symbol rate 1/T comprises a data transmitter (1), a channel (3(1)) of a transmission facility (3) having a plurality of channels (3(1)-3(M), and a data receiver (2) with an equalizer (7) of the decision feedback type. This equalizer comprises a feedback filter (12) with a memory span NT and a feedforward filter (8) which includes a low-pass filter section having a substantially minimum-phase character and an amplitude-frequency characteristic .vertline.W(f).vertline. which has a pronounced maximum .vertline.W(f.sub.m).vertline. for a frequency f.sub.m near to the frequency f=1/((N+1)T) and which is decreasing for frequencies exceeding f.sub.m [FIG. 5A]. Consequently, with respect to conventional dimensionings of the equalizer (7), this achieves an improved transmission quality and/or a reduced complexity of the feedback filter (12).

Abstract: Adaptive filter for producing an echo cancellation signal in a transceiver system arranged for digital communication in the duplex mode via one single pair of conductors, the filter comprising delay means (8) having N terminals for delaying the N most recently transmitted symbols, an addressing circuit (10) having M input terminals (M<N), each of which is coupled to the terminals 1 to M of the delay means, the addressing circuit forming from the signals applied to the input terminals an address for a memory (11) in which for each of these addresses always a first correction signal is stored; a weighting and summing arrangement (9) having N input terminals coupled to the N terminals of the delay means, the arrangement providing a second correction signal which is a weighted sum of all the signals at the input terminals thereof, means (12) for adding together the first correction signal and the second correction signal and an adaptive control loop (13).

Abstract: Adaptive transversal filter for use with three-signal level signals, arranged to cancel shifts in the two extreme signal levels relative to the central signal level, information signaling whether the signal level is the central signal level being coupled to first delay means (2) having N+1 connecting terminals, and information signaling whether the signal level is either one or the other extreme signal level being coupled to second delay means (4) having N+1 connecting terminals and comprising first and second coefficient registers (C.sub.OO -C.sub.ON ; C.sub.O -C.sub.sN) each containing N+1 coefficients; means (8, 9) for always multiplying one of the coefficients by an associated connecting terminal signal of the delay means, means (10) for adding together all the multiplying results obtained for providing a cancellation signal and means for always blocking the signal from a connecting terminal of the second delay means when this signal represents neither the one nor the other extreme signal level.

Abstract: In digital systems clock signals are generated from an external clock reference signal for the purpose of synchronization with the aid of a phase-control loop 1 incorporating a frequency-controllable oscillator 2. In practice synchronization problems occur due to the phase inaccuracy of these clock signals relative to the clock reference.By a two-level control of the oscillator frequency in a plurality of cycles, located within a period of the clock reference signal, using a pulse-width modulator 12, the phase accuracy of a clock signal to be derived from the oscillator output signal is improved.In a preferred embodiment the loop 1 comprises: storage means 16, control means 17 and selection means 18 for providing in accordance with a given phase control strategy a phase-accurate oscillator output signal, this accuracy already being obtained on a small time scale.

Abstract: An arrangement for compensating for non-linear distortion in an input signal to be digitized, comprising an analogue-to-digital converter (2) for converting the input signal into an amplitude-time discrete output signal, means (3) for deriving a set of coefficients which are associated with an orthogonal signal representation of a signal related to the input signal, a memory (4) in which a Table with correction values is stored, means for addressing the memory for reading a correction value from the Table, each of the coefficients determining an address for the memory, means (5) for adding together the correction value and the analogue-to-digital converter output signal for providing a linearized signal, and an adaptive control loop (7,8,16,18) for substituting in the Table the new correction value for the correction value read.

Abstract: A clock signal is derived from a biphase-modulated signal, by means of a controllable clock signal source. The polarity of the received signal is sampled at two sampling instants having a fixed relationship. The polarity samples are added modulo-2 and the resultant signal controls the controllable clock signal source. A false-synchronization detector includes inter alia a modulo-2 adder for comparing polarity samples in consecutive symbol intervals and a counter for counting consecutively equal polarity samples.

Abstract: A transmission arrangement provided with at least one adjustable network whose transfer characteristic between input and output as a function of the frequency .omega. within a prescribed frequency band is approximately equal to C exp [kf(.omega.)], where C is a constant and k a continuously variable parameter.A simple design as well as a large practically feasible adjustment range are obtained because the adjustable network comprises a plurality of channels between input and output and the transfer characteristic of a channel is approximately proportional to a term, different for each channel, from the series of terms of the development of exp [kf(.omega.)] to powers of kf(.omega.), the number of terms corresponding with the number of channels.