Patents by Inventor Koryo Tei

Koryo Tei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7205801
    Abstract: The present invention is to provide a power down circuit, which can configure a wide range of the voltage of the control signal regardless of the fluctuation of the power supply voltage. In the power down circuit 1, the drain of the first N channel MOS transistor M1, into which the control signal PD is input, is connected to the power supply VDD via the resistor R, and at the same time, connected to the gate of the second N channel MOS transistor M2, the source of the second N channel MOS transistor M2 being connected to the gate of the N channel MOS transistor M4, to which the bias voltage VB is supplied, the drain of the N channel MOS transistor M4 being connected to the power supply VDD via the drain of the P channel MOS transistor M3, when the first N channel MOS transistor M1 is turned on/off by the control signal PD, the second N channel MOS transistor M2 is turned off/on, and the bias circuit 2 is operated under a normal condition when it is off, and comes into a power down state when it is on.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: April 17, 2007
    Assignee: Nippon Precision Circuits Inc.
    Inventor: Koryo Tei
  • Patent number: 7161419
    Abstract: An amplification device for a small detection signal has an amplification factor that is variable and also high accuracy offset cancellation. A first switching element selectively connects a normal phase input terminal of an operational amplifier either to a reference potential or to an output terminal of a sensor. An inverse phase input terminal is connected to the reference potential. A capacitor is connected to an output terminal of the operational amplifier and to an output buffer, a second switching element is arranged to selectively connect the capacitor to the reference potential. Resistors are selectively short circuited by switching elements to vary the amplification factor of the operational amplifier.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: January 9, 2007
    Assignee: Seiko NPC Corporation
    Inventors: Koryo Tei, Hiroyuki Kawanishi, Kazuya Yano
  • Publication number: 20060220715
    Abstract: The present invention is to provide a power down circuit, which can configure a wide range of the voltage of the control signal regardless of the fluctuation of the power supply voltage. In the power down circuit 1, the drain of the first N channel MOS transistor M1, into which the control signal PD is input, is connected to the power supply VDD via the resistor R, and at the same time, connected to the gate of the second N channel MOS transistor M2, the source of the second N channel MOS transistor M2 being connected to the gate of the N channel MOS transistor M4, to which the bias voltage VB is supplied, the drain of the N channel MOS transistor M4 being connected to the power supply VDD via the drain of the P channel MOS transistor M3, when the first N channel MOS transistor M1 is turned on/off by the control signal PD, the second N channel MOS transistor M2 is turned off/on, and the bias circuit 2 is operated under a normal condition when it is off, and comes into a power down state when it is on.
    Type: Application
    Filed: October 3, 2005
    Publication date: October 5, 2006
    Inventor: Koryo Tei
  • Publication number: 20050116769
    Abstract: An amplification device of a small detection signal with a multi-element sensor is provided wherein the amplification factor of the operational amplifier can be made variable and also high accuracy offset cancellation and the reduction of noise in low frequency range is possible. A first switching element 31 selectively connects the normal phase input terminal 14 of the operational amplifier 12 either to the reference potential 60 or to the output terminal 2a-2n of the sensor element 1a-1n. The inverse phase input terminal 15 is connected to the reference potential 60 through the resistor 41 and at the same time to the output terminal 16 through the resistor 42, 43. Also one terminal 52 of the capacitor 51 is connected to the output terminal 16 of the operational amplifier 12, the other terminal 53, is connected to the output buffer 13, a second switching element 32 is arranged to selectively connect the terminal 53 to the reference potential 60.
    Type: Application
    Filed: October 12, 2004
    Publication date: June 2, 2005
    Inventors: Koryo Tei, Hiroyuki Kawanishi, Kazuya Yano