Patents by Inventor Kosei OSADA
Kosei OSADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923128Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.Type: GrantFiled: December 6, 2022Date of Patent: March 5, 2024Assignee: ROHM CO., LTD.Inventors: Taketoshi Tanaka, Kosei Osada, Masahiko Arimura
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Publication number: 20230370064Abstract: A gate driver includes a low-voltage circuit configured to be actuated by application of a first voltage and a high-voltage circuit configured to be actuated by application of a second voltage that is higher than the first voltage. The gate driver also includes a transformer and a capacitor connected in series to the transformer. The low-voltage circuit and the high-voltage circuit are connected by the transformer and the capacitor and configured to transmit a signal through the transformer and the capacitor.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Applicant: ROHM CO., LTD.Inventors: Keiji WADA, Bungo TANAKA, Kosei OSADA
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Publication number: 20230361773Abstract: A gate driver configured to apply a drive voltage signal to a gate of a switching element includes a low-voltage circuit chip and a high-voltage circuit chip. The low-voltage circuit chip includes a low-voltage circuit configured to be actuated by application of a first voltage. The high-voltage circuit chip includes a high-voltage circuit configured to be actuated by application of a second voltage that is higher than the first voltage. The gate driver further includes multiple transformer chips connected in series to each other. The low-voltage circuit chip and the high-voltage circuit chip are connected by the multiple transformer chips and configured to transmit a signal through the multiple transformer chips.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Applicant: ROHM CO., LTD.Inventor: Kosei OSADA
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Publication number: 20230317354Abstract: An electronic component includes an insulating layer that has a principal surface, a passive device that includes a low voltage pattern that is formed in the insulating layer and a high voltage pattern that is formed in the insulating layer such as to oppose the low voltage pattern in a normal direction to the principal surface and to which a voltage exceeding a voltage to be applied to the low voltage pattern is to be applied, and a shield conductor layer that is formed in the insulating layer such as to be positioned in a periphery of the high voltage pattern in plan view, shields an electric field formed between the low voltage pattern and the high voltage pattern, and suppresses electric field concentration with respect to the high voltage pattern.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Inventor: Kosei OSADA
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Publication number: 20230298805Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: April 13, 2023Publication date: September 21, 2023Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Patent number: 11742132Abstract: An electronic component includes an insulating layer that has a principal surface, a passive device that includes a low voltage pattern that is formed in the insulating layer and a high voltage pattern that is formed in the insulating layer such as to oppose the low voltage pattern in a normal direction to the principal surface and to which a voltage exceeding a voltage to be applied to the low voltage pattern is to be applied, and a shield conductor layer that is formed in the insulating layer such as to be positioned in a periphery of the high voltage pattern in plan view, shields an electric field formed between the low voltage pattern and the high voltage pattern, and suppresses electric field concentration with respect to the high voltage pattern.Type: GrantFiled: December 14, 2022Date of Patent: August 29, 2023Assignee: ROHM CO., LTD.Inventor: Kosei Osada
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Patent number: 11657953Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: GrantFiled: April 14, 2021Date of Patent: May 23, 2023Assignee: ROHM CO., LTD.Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
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Publication number: 20230124986Abstract: An electronic component includes an insulating layer that has a principal surface, a passive device that includes a low voltage pattern that is formed in the insulating layer and a high voltage pattern that is formed in the insulating layer such as to oppose the low voltage pattern in a normal direction to the principal surface and to which a voltage exceeding a voltage to be applied to the low voltage pattern is to be applied, and a shield conductor layer that is formed in the insulating layer such as to be positioned in a periphery of the high voltage pattern in plan view, shields an electric field formed between the low voltage pattern and the high voltage pattern, and suppresses electric field concentration with respect to the high voltage pattern.Type: ApplicationFiled: December 14, 2022Publication date: April 20, 2023Inventor: Kosei OSADA
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Publication number: 20230107689Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.Type: ApplicationFiled: December 6, 2022Publication date: April 6, 2023Inventors: Taketoshi TANAKA, Kosei OSADA, Masahiko ARIMURA
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Patent number: 11557422Abstract: An electronic component includes an insulating layer that has a principal surface, a passive device that includes a low voltage pattern that is formed in the insulating layer and a high voltage pattern that is formed in the insulating layer such as to oppose the low voltage pattern in a normal direction to the principal surface and to which a voltage exceeding a voltage to be applied to the low voltage pattern is to be applied, and a shield conductor layer that is formed in the insulating layer such as to be positioned in a periphery of the high voltage pattern in plan view, shields an electric field formed between the low voltage pattern and the high voltage pattern, and suppresses electric field concentration with respect to the high voltage pattern.Type: GrantFiled: December 25, 2019Date of Patent: January 17, 2023Assignee: ROHM CO., LTD.Inventor: Kosei Osada
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Patent number: 11545299Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.Type: GrantFiled: October 15, 2018Date of Patent: January 3, 2023Assignee: ROHM CO., LTD.Inventors: Taketoshi Tanaka, Kosei Osada, Masahiko Arimura
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Publication number: 20210233700Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Publication number: 20210193380Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.Type: ApplicationFiled: October 15, 2018Publication date: June 24, 2021Inventors: Taketoshi TANAKA, Kosei OSADA, Masahiko ARIMURA
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Patent number: 11011297Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: GrantFiled: February 27, 2020Date of Patent: May 18, 2021Assignee: ROHM CO., LTD.Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
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Publication number: 20210043361Abstract: An electronic component includes an insulating layer that has a principal surface, a passive device that includes a low voltage pattern that is formed in the insulating layer and a high voltage pattern that is formed in the insulating layer such as to oppose the low voltage pattern in a normal direction to the principal surface and to which a voltage exceeding a voltage to be applied to the low voltage pattern is to be applied, and a shield conductor layer that is formed in the insulating layer such as to be positioned in a periphery of the high voltage pattern in plan view, shields an electric field formed between the low voltage pattern and the high voltage pattern, and suppresses electric field concentration with respect to the high voltage pattern.Type: ApplicationFiled: December 25, 2019Publication date: February 11, 2021Inventor: Kosei OSADA
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Publication number: 20200203058Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: February 27, 2020Publication date: June 25, 2020Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Publication number: 20170287624Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: June 15, 2017Publication date: October 5, 2017Applicant: ROHM CO., LTD.Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
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Patent number: 9697948Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: GrantFiled: November 10, 2014Date of Patent: July 4, 2017Assignee: ROHM CO., LTD.Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
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Publication number: 20150137314Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.Type: ApplicationFiled: November 10, 2014Publication date: May 21, 2015Applicant: ROHM CO., LTD.Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA