Abstract: A road inspection system includes: an inspection determination part that determines, regarding road segments, each of which is a unit obtained by dividing an inspection target road, a need for inspection for the individual road segment; a control part that controls, based on the need for inspection for the individual road segment, measurement of a road surface state(s) of the road performed by a measurement vehicle that is capable of measuring the road surface state(s) or transmission of measured data obtained by the measurement; and a road surface inspection part that analyzes measured data received from the measurement vehicle and performs inspection.

Abstract: A vehicle-mounted apparatus comprises a measurement part capable of measuring, by means of a sensor, a road surface state in which a vehicle travels, a band evaluation part that evaluates a network band between it and a server at a transmission destination of measurement data of the road surface state, an importance calculation part that calculates importance of the measurement data based on a predetermined importance determination policy, a transmission part capable of transmitting the measurement data to the server, and a control part that controls transmission of the measurement data to the server by the transmission part based on evaluation of the network band and the importance of the measurement data.

Abstract: The solid electrolyte material of the present disclosure consists of Li, M1, M2, and I. Here, M1 is at least one selected from the group consisting of Zr and Zn, and M2 is at least one selected from the group consisting of Al, Ga, and In. The battery of the present disclosure comprises a positive electrode, a negative electrode, and an electrolyte layer disposed between the positive electrode and the negative electrode. At least one selected from the group consisting of the positive electrode, the negative electrode, and the electrolyte layer comprises the solid electrolyte material of the present disclosure.

Abstract: The solid electrolyte material of the present disclosure comprises a crystal phase comprising Li, Mg, and X. Here, X is at least one selected from the group consisting of F, Cl, Br, and I, and the crystal phase has a crystal structure belonging to the space group Fm-3m. The battery of the present disclosure comprises a positive electrode, a negative electrode, and an electrolyte layer disposed between the positive electrode and the negative electrode. At least one selected from the group consisting of the positive electrode, the negative electrode, and the electrolyte layer comprises the solid electrolyte material of the present disclosure.

Abstract: An on-vehicle apparatus includes an abnormal section determination part that determines a road section having a road surface on which an abnormality is probably present, based on an output value of a sensor mounted on a vehicle, an image selection part that selects an image(s) including the determined road section from a plurality of images shot at predetermined time intervals by a camera mounted on the vehicle, and a transmission part that is able to transmit the selected image(s) to a predetermined server.

Abstract: A data collection apparatus, including: a data reception part that receives sensor data from a vehicle capable of photographing a road surface, the sensor data being acquired by a sensor mounted on the vehicle; and a control part that evaluates a goodness degree of a road surface photographing environment on a basis of the sensor data and control a transmission from the vehicle of a road surface photographed image on a basis of the goodness degree of the road surface photographing environment.

Abstract: The solid electrolyte material of the present disclosure comprises lithium and a plurality of anion elements. The plurality of anion elements includes antimony and at least one element selected from the group consisting of pnictogen elements excluding antimony, chalcogen elements, and halogen elements. The battery of the present disclosure comprises a positive electrode, a negative electrode, and an electrolyte layer disposed between the positive electrode and the negative electrode, wherein at least one selected from the group consisting of the positive electrode, the negative electrode, and the electrolyte layer contains the solid electrolyte material of the present disclosure.

Abstract: The solid electrolyte material of the present disclosure comprises Li, M, I, and X. M is at least one element selected from the group consisting of Al, Ga, and In. X is at least one element selected from the group consisting of F, O, and S. The battery of the present disclosure comprises a positive electrode, a negative electrode, and an electrolyte layer disposed between the positive electrode and the negative electrode. At least one selected from the group consisting of the positive electrode, the negative electrode, and the electrolyte layer contains the solid electrolyte material of the present disclosure.

Abstract: The solid electrolyte material of the present disclosure contains a crystal phase comprising Li, M, and X. M is at least one selected from the group consisting of Al, Ga, and In. X is at least one selected from the group consisting of Cl, Br, and I. The crystal phase belongs to the space group P21/c. In an X-ray diffraction pattern obtained by X-ray diffraction measurement of the solid electrolyte material, the full width at half maximum of a diffraction peak of a crystal phase assigned to the Miller index (202) crystal plane is greater than or equal to 0.27° and less than or equal to 0.50°.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses. The devices may be fabricated on semiconductor-on-insulator (SOI) wafers utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses. The devices may be fabricated on semiconductor-on-insulator (SOI) wafers utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include in an optoelectronic transceiver comprising photonic and electronic devices from two complementary metal-oxide semiconductor (CMOS) die with different silicon layer thicknesses for the photonic and electronic devices, the CMOS die bonded together by metal contacts: communicating optical signals and electronic signals to and from said optoelectronic transceiver utilizing a received continuous wave optical signal as a source signal. A first of the CMOS die includes the photonic devices and a second includes the electronic devices. Electrical signals may be communicated between electrical devices to the optical devices utilizing through-silicon vias coupled to the metal contacts. The metal contacts may include back-end metals from a CMOS process. The electronic and photonic devices may be fabricated on SOI wafers, with the SOI wafers being diced to form the CMOS die.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include in an optoelectronic transceiver comprising photonic and electronic devices from two complementary metal-oxide semiconductor (CMOS) die with different silicon layer thicknesses for the photonic and electronic devices, the CMOS die bonded together by metal contacts: communicating optical signals and electronic signals to and from said optoelectronic transceiver utilizing a received continuous wave optical signal as a source signal. A first of the CMOS die includes the photonic devices and a second includes the electronic devices. Electrical signals may be communicated between electrical devices to the optical devices utilizing through-silicon vias coupled to the metal contacts. The metal contacts may include back-end metals from a CMOS process. The electronic and photonic devices may be fabricated on SOI wafers, with the SOI wafers being diced to form the CMOS die.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.