Abstract: The solid-state imaging element includes a photoelectric converter, a first separator, and a second separator. The photoelectric converter is configured to perform photoelectric conversion of incident light. The first separator configured to separate the photoelectric converter is formed in a first trench formed from a first surface side. The second separator configured to separate the photoelectric converter is formed in a second trench formed from a second surface side facing a first surface. The present technology is applicable to an individual imaging element mounted on, e.g., a camera and configured to acquire an image of an object.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region being a first-conductivity type, a body region being a second-conductivity type and provided on the drift region, a source region being the first-conductivity type and provided on the body region such that the source region is separated from the drift region, a contact region being the second-conductivity type and provided on the body region. Gate trenches are provided in the first main surface, and extend in a first direction parallel to the first main surface. The contact region is in contact with a first gate trench from both sides in a second direction orthogonal to the first direction and spaced apart from a second gate trench adjacent to the first gate trench in the second direction.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface. The silicon carbide substrate includes an element region including transistors; and a termination region surrounding the element region, the termination region including a first Schottky barrier diode. The silicon carbide substrate includes a first semiconductor region having a first conductivity type; a first surface located between the first main surface and the second main surface; and a second semiconductor region provided on the first surface, the second semiconductor region having a second conductivity type different from the first conductivity type. The second semiconductor region includes a first embedding region provided in the termination region, a first opening being formed in the first embedding region. The first Schottky barrier diode includes a first Schottky electrode provided on the first main surface, the first Schottky electrode overlapping the first opening.

Abstract: A first main surface of a silicon carbide substrate is provided with a first trench and a second trench. The first trench is defined by a first side surface and a first bottom surface. The second trench is defined by a second side surface and a second bottom surface. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region. A first insulating film is in contact with each of the first side surface and the first bottom surface. A gate electrode is provided on the first insulating film. A second insulating film is in contact with each of the second side surface and the second bottom surface. The second impurity region has a connection region electrically connected to the fourth impurity region and extending toward the fourth impurity region along the second side surface.

Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A gate pad faces the first main surface. A drain electrode is in contact with the second main surface. The silicon carbide substrate includes a first impurity region constituting the second main surface and having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, a third impurity region provided on the second impurity region and having the first conductivity type, and a fourth impurity region provided on the third impurity region, constituting the first main surface, and having the second conductivity type. Each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region is located between the gate pad and the drain electrode.

Abstract: A first main surface of a silicon carbide substrate is provided with a first trench and a second trench. The first trench is defined by a first side surface and a first bottom surface. The second trench is defined by a second side surface and a second bottom surface. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, and a fourth impurity region. A first insulating film is in contact with each of the first side surface and the first bottom surface. A gate electrode is provided on the first insulating film. A second insulating film is in contact with each of the second side surface and the second bottom surface. The second impurity region has a connection region electrically connected to the fourth impurity region and extending toward the fourth impurity region along the second side surface.

Abstract: Provided is an illumination device capable of displaying a predetermined design (for example, a logo mark) without using a design film. An illumination device 1 is intended for displaying a predetermined design, and includes: an LED 3; a condenser lens 4 that forms a secondary light source using light emitted from the LED 3; an emission surface 5b from which the secondary light source is emitted; and an optical lens 7 on which the emitted secondary light source is made incident and which has a focal point on the secondary light source. At least one three-dimensional shape of a convex part corresponding to the design and a concave part corresponding to the design is formed on the emission surface 5b.

Abstract: A silicon carbide substrate has at least one of a first structure and a second structure. The first structure is such that a first impurity region is in contact with a second impurity region, a third impurity region is separated from a fourth impurity region by a second drift region, and the second impurity region has a width greater than a width of the fourth impurity region in a direction parallel to a first main surface. The second structure is such that the first impurity region is separated from the second impurity region by a first drift region, the third impurity region is in contact with the fourth impurity region, and the fourth impurity region has a width greater than a width of the second impurity region in the direction parallel to the first main surface.

Abstract: A silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. A gate pad faces the first main surface. A drain electrode is in contact with the second main surface. The silicon carbide substrate includes a first impurity region constituting the second main surface and having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, a third impurity region provided on the second impurity region and having the first conductivity type, and a fourth impurity region provided on the third impurity region, constituting the first main surface, and having the second conductivity type. Each of the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region is located between the gate pad and the drain electrode.

Abstract: The side surface has a first outer end surface. The bottom surface has a first bottom portion continuous to the first outer end surface, and a second bottom portion continuous to the first bottom portion and located on a side opposite to the inner end surface with respect to the first bottom portion. A silicon carbide substrate has a first region and a second region located between the at least one gate trench and a second main surface, and spaced from each other with a drift region being sandwiched therebetween. In a direction parallel to the first outer end surface, a spacing between the first region and the second region located between the first bottom portion and the second main surface is smaller than a spacing between the first region and the second region located between the second bottom portion and the second main surface.

Abstract: A silicon carbide substrate has at least one of a first structure and a second structure. The first structure is such that a first impurity region is in contact with a second impurity region, a third impurity region is separated from a fourth impurity region by a second drift region, and the second impurity region has a width greater than a width of the fourth impurity region in a direction parallel to a first main surface. The second structure is such that the first impurity region is separated from the second impurity region by a first drift region, the third impurity region is in contact with the fourth impurity region, and the fourth impurity region has a width greater than a width of the second impurity region in the direction parallel to the first main surface.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: The side surface has a first outer end surface. The bottom surface has a first bottom portion continuous to the first outer end surface, and a second bottom portion continuous to the first bottom portion and located on a side opposite to the inner end surface with respect to the first bottom portion. A silicon carbide substrate has a first region and a second region located between the at least one gate trench and a second main surface, and spaced from each other with a drift region being sandwiched therebetween. In a direction parallel to the first outer end surface, a spacing between the first region and the second region located between the first bottom portion and the second main surface is smaller than a spacing between the first region and the second region located between the second bottom portion and the second main surface.

Abstract: A first main surface is provided with: a gate trench defined by a first side surface and a first bottom surface; and a source trench defined by a second side surface and a second bottom surface. A silicon carbide substrate includes a drift region, a body region, a source region, a first region, and a second region. The first region is in contact with the second region. A gate insulating film is in contact with the drift region, the body region, and the source region at the first side surface, and is in contact with the drift region at the first bottom surface. A source electrode is in contact with the second region at the second side surface and the second bottom surface.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: A silicon carbide semiconductor device includes a gate insulating film and a gate electrode. A first main surface is provided with a trench defined by a side surface penetrating a third impurity region and a second impurity region to reach a first impurity region, and a bottom provided continuously with the side surface. In a stress test in which a gate voltage of at least one of ?10 V and 20 V is applied to the gate electrode for 100 hours at a temperature of 175° C., where a threshold voltage before the stress test is defined as a first threshold voltage and a threshold voltage after the stress test is defined as a second threshold voltage, an absolute value of a difference between the first threshold voltage and the second threshold voltage is not more than 0.25 V. The second threshold voltage is not less than 2.5 V.

Abstract: An image forming apparatus (1) includes a frame (61) supporting an attached object (23) inserted into an apparatus body (2) and an attachment device (62) fixing the attached object (23) supported by the frame (61). The frame (61) includes a leading end plate (61b) facing to a leading end in an inserting direction of the attached object (23). The attached object (23) includes a fixing pin (65) supported by the leading end plate (61b) in advanceable/retreatable state along the inserting direction and formed connectable to the attached object (23), a biasing member (66) biasing the fixing pin (65) toward the inserting direction and a locking member (67) restricting dropout of the fixing pin (65). The attachment device (62) holds the attached object (23) being connected to the fixing pin (65) and receiving the biasing force of the biasing member (67) at a position gravitated to the leading end plate (61b).

Abstract: An optical scanning device (12) includes cleaning holders (511, 512), light transmitting members (52), a linear member (54), a winding motor (55), and stoppers (56a, 56b). The two cleaning holders (511, 512) are coupled to the linear member (54). The linear member 54 is driven to circulate by the winding motor (55), whereby the two cleaning holders (511, 512) move and each cleaning member slides on a corresponding one of the light transmitting members (52). When the cleaning holders (511, 512) come into contact with the respective stoppers (56a, 56b), the stoppers (56a, 56b) restrict movement of the respective cleaning holders (511, 512) in one of directions of extension of the light transmitting members (52). A contact determining section (913) determines, based on a current value of the winding motor (55), that the cleaning holder (511, 512) has come into contact with the stopper (56a, 56b).

Abstract: A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.