Patents by Inventor Kosuke Yanagidaira
Kosuke Yanagidaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990406Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.Type: GrantFiled: July 8, 2022Date of Patent: May 21, 2024Assignee: KIOXIA CORPORATIONInventors: Kosuke Yanagidaira, Chikaaki Kodama
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Patent number: 11978508Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.Type: GrantFiled: November 11, 2022Date of Patent: May 7, 2024Assignee: Kioxia CorporationInventors: Kosuke Yanagidaira, Hiroshi Tsubouchi, Takeshi Hioka
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Patent number: 11948646Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.Type: GrantFiled: April 24, 2023Date of Patent: April 2, 2024Assignee: Kioxia CorporationInventors: Kosuke Yanagidaira, Mario Sako
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Patent number: 11876647Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.Type: GrantFiled: July 3, 2022Date of Patent: January 16, 2024Assignee: Kioxia CorporationInventors: Kensuke Yamamoto, Kosuke Yanagidaira
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Publication number: 20230410916Abstract: According to one embodiment, a semiconductor memory device includes a first conductor extending in a first direction, bit lines, sense amplifiers, and a second conductor extending in the first direction. A plurality of first memory cells being connected to the first conductor. The bit lines respectively connected to the first memory cells. The first sense amplifiers are respectively connected to a plurality of first bit lines included in the bit lines, each of the first sense amplifiers including a first sense node, and a first transistor connected between the first sense node and a corresponding one of the first bit lines. The second conductor function as gate electrodes of the first transistors included in the first sense amplifiers.Type: ApplicationFiled: July 31, 2023Publication date: December 21, 2023Applicant: KIOXIA CORPORATIONInventor: Kosuke YANAGIDAIRA
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Publication number: 20230377662Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Applicant: Kioxia CorporationInventors: Kosuke YANAGIDAIRA, Hiroshi TSUBOUCHI
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Publication number: 20230290406Abstract: A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1th verification operation is ended after a kth verification operation is ended in the nth write loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nth write loop is supplied to the word line before start of the k+1th verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1th verification operation is shorter than a time from start of the first verification operation to end of the kth verification operation in the nth write loop.Type: ApplicationFiled: May 16, 2023Publication date: September 14, 2023Inventor: Kosuke YANAGIDAIRA
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Patent number: 11756628Abstract: A semiconductor memory device includes a first conductor extending in a first direction, bit lines, sense amplifiers, and a second conductor extending in the first direction. A plurality of first memory cells being connected to the first conductor. The bit lines respectively connected to the first memory cells. The first sense amplifiers are respectively connected to a plurality of first bit lines included in the bit lines, each of the first sense amplifiers including a first sense node, and a first transistor connected between the first sense node and a corresponding one of the first bit lines. The second conductor function as gate electrodes of the first transistors included in the first sense amplifiers.Type: GrantFiled: May 21, 2021Date of Patent: September 12, 2023Assignee: KIOXIA CORPORATIONInventor: Kosuke Yanagidaira
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Patent number: 11756632Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.Type: GrantFiled: December 19, 2022Date of Patent: September 12, 2023Assignee: Kioxia CorporationInventors: Kosuke Yanagidaira, Hiroshi Tsubouchi
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Publication number: 20230260579Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: Kosuke YANAGIDAIRA, Mario SAKO
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Patent number: 11694746Abstract: A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1th verification operation is ended after a kth verification operation is ended in the nth write loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nth write loop is supplied to the word line before start of the k+1th verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1th verification operation is shorter than a time from start of the first verification operation to end of the kth verification operation in the nth write loop.Type: GrantFiled: February 25, 2021Date of Patent: July 4, 2023Assignee: KIOXIA CORPORATIONInventor: Kosuke Yanagidaira
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Patent number: 11670383Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through the second and third transistors.Type: GrantFiled: January 13, 2022Date of Patent: June 6, 2023Assignee: KIOXIA CORPORATIONInventors: Kosuke Yanagidaira, Mario Sako
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Publication number: 20230119989Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Applicant: Kioxia CorporationInventors: Kosuke YANAGIDAIRA, Hiroshi TSUBOUCHI
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Publication number: 20230062330Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.Type: ApplicationFiled: November 11, 2022Publication date: March 2, 2023Applicant: Kioxia CorporationInventors: Kosuke YANAGIDAIRA, Hiroshi TSUBOUCHI, Takeshi HIOKA
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Patent number: 11562795Abstract: A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.Type: GrantFiled: June 30, 2021Date of Patent: January 24, 2023Assignee: KIOXIA CORPORATIONInventors: Kosuke Yanagidaira, Hiroshi Tsubouchi
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Patent number: 11527284Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.Type: GrantFiled: March 11, 2021Date of Patent: December 13, 2022Assignee: Kioxia CorporationInventors: Kosuke Yanagidaira, Hiroshi Tsubouchi, Takeshi Hioka
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Patent number: 11500770Abstract: According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.Type: GrantFiled: July 7, 2020Date of Patent: November 15, 2022Assignee: Kioxia CorporationInventors: Kosuke Yanagidaira, Shouichi Ozaki
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Publication number: 20220344256Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Applicant: KIOXIA CORPORATIONInventors: Kosuke YANAGIDAIRA, Chikaaki KODAMA
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Publication number: 20220337457Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal.Type: ApplicationFiled: July 3, 2022Publication date: October 20, 2022Inventors: Kensuke YAMAMOTO, Kosuke YANAGIDAIRA
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Patent number: 11423980Abstract: A semiconductor storage device includes a first plane storing user data and system information, a second plane storing the user data and the system information, a first latch circuit storing even-numbered bit data of the system information read from the first plane, a second latch circuit storing odd-numbered bit data of the system information read from the second plane, and a sequencer. The sequencer executes in parallel a first process of reading out the even-numbered bit data of the system information from the first plane and storing the read data in the first latch circuit and a second process of reading out the odd-numbered bit data of the system information from the second plane and storing the read data in the second latch circuit.Type: GrantFiled: February 24, 2021Date of Patent: August 23, 2022Assignee: KIOXIA CORPORATIONInventors: Yuki Shimizu, Kosuke Yanagidaira