Patents by Inventor Kotaro Esaki
Kotaro Esaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11455993Abstract: An electronic device controlling system that provides an instruction via voice for an operation of a speech recognition-capable electronic device includes a control device and a voice output device capable of communicating with the control device. The control device includes a first input unit that receives, from an operator, a first input to which a first operation instruction for the speech recognition-capable electronic device is assigned; and a transmitter that, when the first input unit receives the first input, transmits, to the voice output device, first information for communication corresponding to the first operation instruction assigned to the first input. The voice output device includes a receiver that receives the first information for communication from the control device; and an output unit that, when the receiver receives the first information for communication, outputs a first voice for the first operation instruction based on the first information for communication.Type: GrantFiled: March 5, 2020Date of Patent: September 27, 2022Assignee: SOCIONEXT INC.Inventor: Kotaro Esaki
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Publication number: 20200366771Abstract: A mobile terminal that operates on a secondary battery, the mobile terminal including: a power receiver that wirelessly receives electric power, and supplies the secondary battery with the electric power received; a display unit that provides a display indicating that the power receiver is receiving the electric power; and a display controller that causes the display unit to provide the display differently in accordance with magnitude of the electric power received by the power receiver.Type: ApplicationFiled: August 4, 2020Publication date: November 19, 2020Inventor: Kotaro ESAKI
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Publication number: 20200202861Abstract: An electronic device controlling system that provides an instruction via voice for an operation of a speech recognition-capable electronic device includes a control device and a voice output device capable of communicating with the control device. The control device includes a first input unit that receives, from an operator, a first input to which a first operation instruction for the speech recognition-capable electronic device is assigned; and a transmitter that, when the first input unit receives the first input, transmits, to the voice output device, first information for communication corresponding to the first operation instruction assigned to the first input. The voice output device includes a receiver that receives the first information for communication from the control device; and an output unit that, when the receiver receives the first information for communication, outputs a first voice for the first operation instruction based on the first information for communication.Type: ApplicationFiled: March 5, 2020Publication date: June 25, 2020Inventor: Kotaro ESAKI
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Publication number: 20130322546Abstract: A stream generation apparatus includes: a first processing unit which performs, on headers and quantized data, first processing including at least variable-length coding on the headers; a first transfer control unit which transfers the headers on which the first processing has been performed to a first storage area and the quantized data on which the first processing has been performed to a second storage area; a second transfer control unit which obtains headers and quantized data items for a predetermined unit from the first storage area and the second storage area, respectively; and a second processing unit which performs, on the headers and quantized data items for the predetermined unit, second processing including at least compression coding on the quantized data items for the predetermined unit. The second processing unit generates a stream including the compression coded headers followed by the compression coded quantized data.Type: ApplicationFiled: August 7, 2013Publication date: December 5, 2013Applicant: Panasonic CorporationInventors: Kotaro ESAKI, Kohei OKADA
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Publication number: 20120263230Abstract: An image coding apparatus includes a binarizing unit which generate binary data corresponding to quantized data, and an arithmetic coding unit which generate a stream corresponding to the binary data. In the image coding apparatus, one or both of the binarizing and the arithmetic coding are performed. The binarizing is performed by the binarizing unit alternately on first quantized data and second quantized data, using a time division technique. The arithmetic coding is performed by the arithmetic coding unit alternately on first binary data and second binary data, using the time division technique.Type: ApplicationFiled: June 27, 2012Publication date: October 18, 2012Applicant: PANASONIC CORPORATIONInventors: Kotaro ESAKI, Tsutomu HASHIMOTO
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Publication number: 20120051433Abstract: While temporal and spatial direct modes are both supported, the amount of temporarily-stored direct-mode prediction information is reduced, thereby reducing the memory bus bandwidth. A motion information generator combines a motion vector for an anchor block with the number of a reference picture of the anchor block, thereby generates motion information of the pixel block. A still-state determination unit determines whether or not the pixel block is considered still based on the motion vector for the anchor block and on the number of the reference picture. A selector selectively stores in a memory either an output of the motion information generator or a determination result of the still-state determination unit as direct-mode prediction information of the pixel block. A motion vector predictor predicts a motion vector for the pixel block in direct mode based on the direct-mode prediction information stored in the memory.Type: ApplicationFiled: November 9, 2011Publication date: March 1, 2012Applicant: Panasonic CorporationInventors: Mikiko Roji, Masayasu Iguchi, Kotaro Esaki, Hiroshi Amano
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Patent number: 8009738Abstract: A data holding apparatus of the present invention is a data holding apparatus a data holding apparatus used for image processing in which an image is coded or decoded, on a macroblock basis, based on a field structure or a frame structure selected on a macroblock pair basis. This data holding apparatus includes: a current register which holds a parameter set of a current macroblock to be coded or decoded; and registers which respectively hold parameter sets of macroblocks having neighboring relationships with a current macroblock, and at least one of the registers selectively holds, in sequence, parameter sets of respective different macroblocks having the neighboring relationships, one parameter set at a time.Type: GrantFiled: January 3, 2006Date of Patent: August 30, 2011Assignee: Panasonic CorporationInventor: Kotaro Esaki
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Publication number: 20110122952Abstract: A motion estimation device configured to estimate motion for blocks included in an input picture using a reference picture includes an internal reference memory configured to store the reference picture transferred from outside the motion estimation device; a motion estimator configured to estimate motion information for a target block that is a block of the input picture and where motion is to be estimated, using pixel data of the reference picture stored in the internal reference memory; a motion compensator configured to perform motion compensation for the target block using the motion information estimated by the motion estimator; and a reference memory manager configured to control the internal reference memory. The reference memory manager is configured to control the internal reference memory to store a luminance reference picture and a color-difference reference picture as the reference picture.Type: ApplicationFiled: January 31, 2011Publication date: May 26, 2011Applicant: PANASONIC CORPORATIONInventors: Kotaro ESAKI, Masayasu IGUCHI, Takeshi FURUTA, Hiroshi AMANO
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Patent number: 7471338Abstract: In order to reduce the circuit scale and the manufacturing cost by decreasing the amount of data to be stored, a synchronizing signal data generating circuit outputs, at each timing, relative synchronizing signal data showing the ratio of a synchronizing signal level to an amplitude level of the synchronizing signal, a multiplier multiplies synchronizing signal amplitude level data, a divider divides by the maximum value N of image signal data which can be outputted from the synchronizing signal data generating circuit, thereby the synchronizing signal data showing actual synchronizing signal level is provided, and an adder adds input image signal data thereto, whereby output image signal data, in which the synchronizing signal data is superposed on the input image signal data, is generated.Type: GrantFiled: January 5, 2005Date of Patent: December 30, 2008Assignee: Panasonic CorporationInventor: Kotaro Esaki
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Publication number: 20060256872Abstract: A filtering characteristic error concealing apparatus according to the present invention has: a calculation unit whch calculates a characteristic value of each block included in a picture, the characteristic value being used in deblocking filtering for the bock and representing strength of the deblocking filtering; a control unit which controls the calculation unit (i) to start and terminate the calculation for the block, and (ii) to designate locations of boundaries of the block; an error detection unit which detects an error related to the calculation; and a mask circuit which conceals deblocking filtering that is performed for each of a block for which the error is detected and blocks subsequent to the block with the error, when the error is detected.Type: ApplicationFiled: May 11, 2006Publication date: November 16, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Kotaro Esaki
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Publication number: 20060153302Abstract: A data holding apparatus of the present invention is a data holding apparatus a data holding apparatus used for image processing in which an image is coded or decoded, on a macroblock basis, based on a field structure or a frame structure selected on a macroblock pair basis. This data holding apparatus includes: a current register which holds a parameter set of a current macroblock to be coded or decoded; and registers which respectively hold parameter sets of macroblocks having neighboring relationships with a current macroblock, and at least one of the registers selectively holds, in sequence, parameter sets of respective different macroblocks having the neighboring relationships, one parameter set at a time.Type: ApplicationFiled: January 3, 2006Publication date: July 13, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Kotaro Esaki
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Publication number: 20050231638Abstract: In order to reduce the circuit scale and the manufacturing cost by decreasing the amount of data to be stored, a synchronizing signal data generating circuit outputs, at each timing, relative synchronizing signal data showing the ratio of a synchronizing signal level to an amplitude level of the synchronizing signal, a multiplier multiplies synchronizing signal amplitude level data, a divider divides by the maximum value N of image signal data which can be outputted from the synchronizing signal data generating circuit, thereby the synchronizing signal data showing actual synchronizing signal level is provided, and an adder adds input image signal data thereto, whereby output image signal data, in which the synchronizing signal data is superposed on the input image signal data, is generated.Type: ApplicationFiled: January 5, 2005Publication date: October 20, 2005Inventor: Kotaro Esaki
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Publication number: 20050078675Abstract: A data sequence of PES (packetized elementary stream) format included in received TS (transport stream) format data is recognized in a TD (transport decoder) by detecting a PES header based on a TS header and TS data. In PES mode, information indicative of the place in the data sequence where the detected PES header exists in PES data is transmitted from the TD to an AVD (AV decoder) together with the PES header. In ES mode, the detected PES header is removed in the TD, the received TS data is converted to ES format data, and the ES format data is transmitted to the AV decoder.Type: ApplicationFiled: October 7, 2004Publication date: April 14, 2005Inventors: Tomoki Nishikawa, Kotaro Esaki