Patents by Inventor Kotaro Fujii
Kotaro Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002894Abstract: A photosensor includes: a support; a thermoelectric conversion material section that is disposed on a first main surface of the support and that includes a plurality of first material layers each having an elongated shape, a plurality of second material layers each having electrical conductivity and an elongated shape, and an insulating film, the first material layers and the second material layers each being configured to convert thermal energy into electrical energy; a heat sink that is disposed on a second main surface of the support and along an outer edge of the support; a light-absorbing film that is disposed in a region surrounded by inner edges of the heat sink as viewed in a thickness direction of the support so as to form temperature differences on the first main surface of the support in longitudinal directions of the first material layers.Type: GrantFiled: January 3, 2022Date of Patent: June 4, 2024Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kotaro Hirose, Masahiro Adachi, Yoshiyuki Yamamoto, Shunsuke Fujii, Fuminori Mitsuhashi
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Patent number: 12002777Abstract: According to one or more embodiments, a semiconductor device includes a first substrate and a second substrate. The first substrate includes a first metal layer and a first insulating layer. The first insulating layer surrounds the first metal layer. The second substrate includes a second metal layer, a second insulating layer, and a first conducive body. The second metal layer is in contact with the first metal layer. The second insulating layer surrounds the second metal layer and is in contact with the first insulating layer. A part of the first conductive body is in the second metal layer and extends in a first direction toward the first metal layer.Type: GrantFiled: August 30, 2021Date of Patent: June 4, 2024Assignee: Kioxia CorporationInventors: Kotaro Fujii, Shinya Watanabe
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Publication number: 20240167131Abstract: The present invention has as its technical problem to obtain an alloy having a low thermal coefficient characteristic or a negative coefficient of thermal expansion in the vicinity of 600 to 800° C. The controlled expansion alloy of the present invention contains, by wt %, Fe: 20 to 50%, Ni: 0 to 25%, and Cr: 0 to 30% and has a balance of Co and impurities.Type: ApplicationFiled: March 17, 2022Publication date: May 23, 2024Applicant: SHINHOKOKU MATERIAL CORPORATIONInventors: Hiromichi FUJII, Shingo MATSUMURA, Haruyasu OHNO, Kotaro ONA
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Patent number: 11983940Abstract: An autonomous vehicle that moves automatically without any driver's manipulation. The autonomous vehicle includes a vehicle body including a deck, and an action-inducing device for inducing an action of a person who is a user of the autonomous vehicle or a non-user around the autonomous vehicle. The action-inducing device including an image-capturing device for capturing the person, and an information presentation device for presenting action-inducing information, to thereby induce the person to take the action.Type: GrantFiled: April 23, 2021Date of Patent: May 14, 2024Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHAInventors: Kotaro Ogura, Takehiro Ogawa, Yoshiki Kuranuki, Hokuto Fujii
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Patent number: 11956959Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: GrantFiled: May 24, 2021Date of Patent: April 9, 2024Assignee: Kioxia CorporationInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Publication number: 20240096795Abstract: A semiconductor storage device according to an embodiment includes a first wiring, a second wiring, a first insulating layer, a first insulator, and a conductor. The first insulating layer has a first portion, a second portion, and a third portion. The first portion is stacked on the first wiring. The second portion is stacked on the second wiring. The third portion is on the opposite side of the first wiring and the second wiring with respect to the first portion and the second portion.Type: ApplicationFiled: March 13, 2023Publication date: March 21, 2024Applicant: Kioxia CorporationInventor: Kotaro FUJII
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Patent number: 11672117Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: GrantFiled: January 7, 2021Date of Patent: June 6, 2023Assignee: Kioxia CorporationInventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
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Publication number: 20220302055Abstract: According to one or more embodiments, a semiconductor device includes a first substrate and a second substrate. The first substrate includes a first metal layer and a first insulating layer. The first insulating layer surrounds the first metal layer. The second substrate includes a second metal layer, a second insulating layer, and a first conducive body. The second metal layer is in contact with the first metal layer. The second insulating layer surrounds the second metal layer and is in contact with the first insulating layer. A part of the first conductive body is in the second metal layer and extends in a first direction toward the first metal layer.Type: ApplicationFiled: August 30, 2021Publication date: September 22, 2022Inventors: Kotaro FUJII, Shinya WATANABE
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Publication number: 20220115684Abstract: A solid electrolyte having high electrical conductivity even in a low-temperature region is provided. A solid electrolyte containing a hexagonal perovskite-related compound, in which the compound is a compound represented by the following general formula (1), and an electrolyte layer and a battery using the solid electrolyte are disclosed. Ba7-?Nb(4?x-y)Mo(1+x)MyO(20+z) (1), in the formula (1), M is a cation of at least one element; a represents a Ba deficiency amount and represents a value of 0 or more and 0.5 or less, x represents a value of ?1.1 or more and 1.1 or less, y represents a value of 0 or more and 1.1 or less, and z represents an oxygen non-stoichiometry and represents a value of ?2.0 or more and 2.0 or less, provided that in the formula (1), |x|+y?0.01 is satisfied.Type: ApplicationFiled: January 24, 2020Publication date: April 14, 2022Applicant: Tokyo Institute of TechnologyInventors: Masatomo Yashima, Takafumi Tsujiguchi, Kotaro Fujii, Eiki Niwa, Yuichi Sakuda, Taito Murakami, Yuta Yasui, Yugo Kikuchi, Yuki Suzuki
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Publication number: 20210280603Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Applicant: Toshiba Memory CorporationInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Patent number: 11088162Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.Type: GrantFiled: February 25, 2019Date of Patent: August 10, 2021Assignee: Toshiba Memory CorporationInventors: Kotaro Fujii, Satoshi Nagashima, Yumi Nakajima
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Patent number: 11049878Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: GrantFiled: July 14, 2020Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Patent number: 11018150Abstract: A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third electrode film separated from the second electrode film in the first direction, a fourth electrode film separated from the third electrode film in the first direction, and a first and a second semiconductor members extending in the first direction. The second electrode film includes a first conductive portion, an insulating portion, and a second conductive portion arranged along a second direction. The first semiconductor member pierces the first, third and fourth electrode films and the insulating portion of the second electrode film. The second semiconductor member pierces the first, third and fourth electrode films, and the first conductive portion or the second conductive portion of the second electrode film.Type: GrantFiled: September 11, 2018Date of Patent: May 25, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kotaro Fujii, Yasuhiro Uchiyama, Masaru Kito
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Publication number: 20210126003Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: ApplicationFiled: January 7, 2021Publication date: April 29, 2021Applicant: Toshiba Memory CorporationInventors: Kotaro FUJII, Jun FUJIKI, Shinya ARAI
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Patent number: 10937803Abstract: According to one embodiment, a semiconductor storage device includes a stacked body, a first semiconductor layer extending in the stacked body, a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer, a second conductor layer disposed above the stacked body, a second semiconductor layer extending through the second conductor layer, a third conductor layer disposed between the second semiconductor layer and the second conductor layer, a first insulator layer disposed above the third conductor layer, and a second insulator layer including a first portion disposed between the second semiconductor layer and the third conductor layer and a second portion disposed between the second semiconductor layer and the first insulator layer. A diameter of the second insulator layer is larger in the second portion than in the first portion.Type: GrantFiled: August 2, 2019Date of Patent: March 2, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takayuki Kashima, Kohei Nyui, Kotaro Fujii, Hiroyuki Yamasaki
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Patent number: 10923490Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: GrantFiled: January 9, 2020Date of Patent: February 16, 2021Assignee: Toshiba Memory CorporationInventors: Kotaro Fujii, Jun Fujiki, Shinya Arai
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Publication number: 20200343264Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Applicant: Toshiba Memory CorporationInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Publication number: 20200273876Abstract: According to one embodiment, a semiconductor storage device includes a stacked body, a first semiconductor layer extending in the stacked body, a first charge storage layer disposed between the plurality of first conductor layers and the first semiconductor layer, a second conductor layer disposed above the stacked body, a second semiconductor layer extending through the second conductor layer, a third conductor layer disposed between the second semiconductor layer and the second conductor layer, a first insulator layer disposed above the third conductor layer, and a second insulator layer including a first portion disposed between the second semiconductor layer and the third conductor layer and a second portion disposed between the second semiconductor layer and the first insulator layer. A diameter of the second insulator layer is larger in the second portion than in the first portion.Type: ApplicationFiled: August 2, 2019Publication date: August 27, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takayuki KASHIMA, Kohei NYUI, Kotaro FUJII, Hiroyuki YAMASAKI
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Patent number: 10756104Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.Type: GrantFiled: September 12, 2018Date of Patent: August 25, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
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Publication number: 20200144278Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film, a plurality of first electrode films provided above the first conductive film and stacked to be separated from each other, a semiconductor member extending in a stacking direction of the plurality of first electrode films, and a charge storage member provided between the semiconductor member and one of the plurality of first electrode films. The first conductive film includes a main portion disposed at least below the plurality of first electrode films, and a fine line portion extending from the main portion toward an end surface side of the semiconductor substrate. A width of the fine line portion is narrower than a width of the main portion.Type: ApplicationFiled: January 9, 2020Publication date: May 7, 2020Applicant: Toshiba Memory CorporationInventors: Kotaro Fujii, Jun Fujiki, Shinya Arai