Abstract: Backup system and method that can determine a backup destination in consideration of disaster are provided. There are provided: a data acquisition unit 110 that acquires disaster information, network information, and node information; a replication group construction unit 130 that generates, based on the disaster information, and the like, replication group information including association information between a first node that stores original data and one or more second nodes that are candidates for backup destination of the original data, and saves the replication group information in a storage unit 120; a replication destination node calculation unit 140 that, when executing backup of the original data, calculates the second node as backup destination from the replication group; and a replication processing unit 230 that replicates and stores the original data into the storage of the second node.

Abstract: A processing device includes a processor configured to output a memory access instruction issued by a process executed on a virtual machine and a virtual address targeted by the memory access instruction. The processor is configured to perform first translation of translating the virtual address into a real address of a virtual memory. The processor is configured to perform second translation of translating the real address into a physical address of a physical memory. The processor is configured to determine, based on the memory access instruction and an access permission attribute of the real address, whether an access permission violation occurs. The processor is configured to perform, upon determining that an access permission violation occurs, retranslation of translating the virtual address into the real address. The processor is configured to record the virtual address and the real address obtained by the retranslation in a log area of a memory.

Abstract: A processing device includes a processor configured to output a memory access instruction issued by a process executed on a virtual machine and a virtual address targeted by the memory access instruction. The processor is configured to perform first translation of translating the virtual address into a real address of a virtual memory. The processor is configured to perform second translation of translating the real address into a physical address of a physical memory. The processor is configured to determine, based on the memory access instruction and an access permission attribute of the real address, whether an access permission violation occurs. The processor is configured to perform, upon determining that an access permission violation occurs, retranslation of translating the virtual address into the real address. The processor is configured to record the virtual address and the real address obtained by the retranslation in a log area of a memory.

Abstract: An arithmetic processing device includes: first prediction units which output branch prediction information of a fetched conditional branch instruction based on past branch history information of conditional branch instructions; a second prediction unit which stores a branch taken consecutive number of times and a branch not-taken consecutive number of times to a pattern information storage unit, and outputs branch prediction information of a fetched conditional branch instruction based on the past branch taken consecutive number of times or branch not-taken consecutive number of times stored; selecting units which selectively output the branch prediction information output from the first prediction units or the second prediction unit; and a selector which outputs a next instruction address of the conditional branch instruction or a branch target address of the conditional branch instruction to an instruction fetch unit in accordance with the branch prediction information output by the selecting units.

Abstract: An arithmetic processing device includes: first prediction units which output branch prediction information of a fetched conditional branch instruction based on past branch history information of conditional branch instructions; a second prediction unit which stores a branch taken consecutive number of times and a branch not-taken consecutive number of times to a pattern information storage unit, and outputs branch prediction information of a fetched conditional branch instruction based on the past branch taken consecutive number of times or branch not-taken consecutive number of times stored; selecting units which selectively output the branch prediction information output from the first prediction units or the second prediction unit; and a selector which outputs a next instruction address of the conditional branch instruction or a branch target address of the conditional branch instruction to an instruction fetch unit in accordance with the branch prediction information output by the selecting units.