Patents by Inventor Kotb JABEUR
Kotb JABEUR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11621026Abstract: A method for compensating for external magnetic fields in memory devices that includes positioning at least one external magnetic field sensing element adjacent to at least one array of memory cells, wherein a write driver is in electrical communication with at least one external magnetic field sensing element and at least one array of memory cells. The at least one external magnetic field sensing element is monitored for signals indicative of the present of an external magnetic field. The write current to the at least one array of memory cells can be adjusted by trimming the write driver to operate the memory device while compensating for the external magnetic field.Type: GrantFiled: December 1, 2020Date of Patent: April 4, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dimitri Houssameddine, Kotb Jabeur, Eric Robert Joseph Edwards
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Publication number: 20220172763Abstract: A method for compensating for external magnetic fields in memory devices that includes positioning at least one external magnetic field sensing element adjacent to at least one array of memory cells, wherein a write driver is in electrical communication with at least one external magnetic field sensing element and at least one array of memory cells. The at least one external magnetic field sensing element is monitored for signals indicative of the present of an external magnetic field. The write current to the at least one array of memory cells can be adjusted by trimming the write driver to operate the memory device while compensating for the external magnetic field.Type: ApplicationFiled: December 1, 2020Publication date: June 2, 2022Inventors: Dimitri Houssameddine, Kotb Jabeur, Eric Robert Joseph Edwards
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Patent number: 11289644Abstract: A magnetic tunnel junction (MTJ) device includes a cylindrically-shaped pillar structure and a first ferromagnetic layer disposed on at least a portion of the pillar structure. The first ferromagnetic layer exhibits a magnetization that is changeable in the presence of at least one of an applied bias and heat. The MTJ device further includes a dielectric barrier disposed on at least a portion of the first ferromagnetic layer and a second ferromagnetic layer disposed on at least a portion of the dielectric barrier. The second ferromagnetic layer exhibits a magnetization that is fixed. The MTJ device is configured such that the first and second ferromagnetic layers and the dielectric barrier concentrically surround the pillar structure.Type: GrantFiled: December 19, 2019Date of Patent: March 29, 2022Assignee: International Business Machines CorporationInventors: Kotb Jabeur, Daniel Worledge, Jonathan Z. Sun, Pouya Hashemi
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Publication number: 20210193910Abstract: A magnetic tunnel junction (MTJ) device includes a cylindrically-shaped pillar structure and a first ferromagnetic layer disposed on at least a portion of the pillar structure. The first ferromagnetic layer exhibits a magnetization that is changeable in the presence of at least one of an applied bias and heat. The MTJ device further includes a dielectric barrier disposed on at least a portion of the first ferromagnetic layer and a second ferromagnetic layer disposed on at least a portion of the dielectric barrier. The second ferromagnetic layer exhibits a magnetization that is fixed. The MTJ device is configured such that the first and second ferromagnetic layers and the dielectric barrier concentrically surround the pillar structure.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Inventors: Kotb Jabeur, Daniel Worledge, Jonathan Z. Sun, Pouya Hashemi
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Patent number: 11037645Abstract: Memory devices incorporating selective boosting techniques and methods for managing memory devices incorporating selective boosting techniques. One or more bit cells of a memory device are tested during a test phase and one or more addresses of one or more weak bit cells are stored in a non-volatile weak bit address memory within the memory device.Type: GrantFiled: June 25, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Kotb Jabeur, John Kenneth DeBrosse
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Patent number: 11024355Abstract: An MRAM bitline write control circuit including an MRAM array of a plurality of MTJ cells. Each MTJ cell is connected to a bitline between a bitline transfer gate and a transfer device. Each transfer device is connected to a sourceline and a sourceline transfer gate. A master bitline is connected to each bitline transfer gate. A first bitline control transistor is connected to VDD and to a source follower transistor that is connected to the master bitline and a gate connected to a write 0 bias voltage. A second bitline control transistor is connected to VSS and to the master bitline. A selected MTJ cell is biased to write a 0 when the transfer device, the bitline transfer gate and the source line transfer gate, associated with the selected MTJ cell, are enabled and the first bitline control transistor is enabled to connect the source follower transistor to VDD.Type: GrantFiled: January 31, 2020Date of Patent: June 1, 2021Assignee: International Business Machines CorporationInventors: Kotb Jabeur, Ryan A. Jurasek
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Publication number: 20200411128Abstract: Memory devices incorporating selective boosting techniques and methods for managing memory devices incorporating selective boosting techniques. One or more bit cells of a memory device are tested during a test phase and one or more addresses of one or more weak bit cells are stored in a non-volatile weak bit address memory within the memory device.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: Kotb Jabeur, John Kenneth DeBrosse
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Patent number: 10839935Abstract: A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.Type: GrantFiled: February 5, 2019Date of Patent: November 17, 2020Assignee: International Business Machines CorporationInventors: Daniel Worledge, John K. DeBrosse, Kotb Jabeur, Matthew R. Wordeman
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Patent number: 10741232Abstract: A memory device comprising a memory array of a plurality of memory bit cells; a read reference system comprising four or more reference memory bit cells in a reference column of the memory array; wherein a first bit cell of the reference memory bit cells is always selected; wherein a bitline of the first bit cell of the reference memory bit cells is connected to a bitline of a first subset of the reference memory bit cells, and a select line of the first bit cell of the reference memory bit cells is connected to a reference select signal; wherein a select line of each of the first subset of the reference memory bit cells and a second subset of the reference memory bit cells are coupled together; and wherein a bitline blref of the second subset of the reference memory bit cells outputs a read reference signal.Type: GrantFiled: June 25, 2019Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Kotb Jabeur, John Kenneth DeBrosse
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Publication number: 20200250029Abstract: A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.Type: ApplicationFiled: February 5, 2019Publication date: August 6, 2020Inventors: Daniel Worledge, John K. DeBrosse, Kotb Jabeur, Matthew R. Wordeman
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Publication number: 20150036415Abstract: The invention concerns a memory device comprising: a memory cell having at least one resistive memory element (202) with first, second and third terminals (A, B, C), a resistance between the third terminal (C) and one or both of the first and second terminals being programmable to have one of at least two resistive states (Rmin, Rmax); and control circuitry (204) adapted: during a write phase of the resistive memory element, to program the resistive state by driving a current between the first and second terminals; and during a read phase of the resistive memory element, to apply a voltage between the third terminal and at least one of the first and second terminals to generate a current through the first resistive memory element that is proportional to the programmed resistive state.Type: ApplicationFiled: July 29, 2014Publication date: February 5, 2015Inventors: Grégory DI PENDINA, Kotb JABEUR