Patents by Inventor Kou Shimomura

Kou Shimomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5592019
    Abstract: A semiconductor device in a vertical surface mount package, reduced in size and having a higher heat radiating capacity, a method of producing the semiconductor device, and a semiconductor module. Leads of a first lead frame and leads of a second lead frame are parallel to each other and at least a portion of the leads overlap leads of the other lead frame when geometrically projected on them. An inner lead may extend out from the semiconductor package or the back side of a die pad in the semiconductor package may be exposed. The invention allows more outer leads to be used and makes it possible to reduce the size of the semiconductor device and to achieve high density mounting.
    Type: Grant
    Filed: April 4, 1995
    Date of Patent: January 7, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Kisamitsu Ono, Kou Shimomura, Hideyuki Ichiyama
  • Patent number: 5196917
    Abstract: A carrier tape includes an insulating film supporting a plurality of leads. The film has a center device hole for receiving a semiconductor chip therein, a plurality of outer lead holes formed at the periphery of the center device hole, a lead supporting portion positioned between the center device hole and the outer lead holes, and a link portion positioned between a pair of adjacent outer lead holes and connected to the lead supporting portion for directing the flow of molten resin during encapsulation of the semiconductor chip. The link portion includes an opening or recess. The plurality of leads of the carrier tape are supported on the lead supporting of the film, with one end portion of each lead projecting into the center device hole of the film. During manufacture, a semiconductor chip having a plurality of electrodes is positioned within the center device hole, and the leads are electrically connected to respective electrodes of the semiconductor chip.
    Type: Grant
    Filed: December 4, 1989
    Date of Patent: March 23, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tetsuya Ueda, Kou Shimomura, Osamu Nakagawa, Seiji Takemura, Kazunari Michii
  • Patent number: 5034436
    Abstract: A semiconductor sealing epoxy resin composition includes a flexibilizer which is a previous reactant between a denatured silicone oil having epoxy groups and a phenol novolak resin, a novolak type of epoxy resin, a hardening agent, an accelerator, a filler, a die lubricant, and a surface treatment agent. This composition has a heat and moisture resistance needs for a semiconductor sealing material, and as well as a low elastic modulus.
    Type: Grant
    Filed: November 9, 1990
    Date of Patent: July 23, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Ichiro Takahashi, Hiromi Ito, Goro Okamoto, Kazuo Okahashi, Kou Shimomura
  • Patent number: 4824801
    Abstract: A polysilicon film is provided in a first region provided with a bonding pad on a silicon substrate and a second region apart from the first region and surrounding the first region, an aluminum film serving as a bonding pad is provided on the polysilicon film in the first region, a PSG (Phospho-Silicate Glass) film is provided on the polysilicon film in the second region, and an insulating protective film including no phosphorus is provided between the aluminum film and the PSG film.
    Type: Grant
    Filed: September 9, 1987
    Date of Patent: April 25, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Kawashimo, Kouichi Nakagawa, Kou Shimomura