Patents by Inventor Kouhei Nagaya

Kouhei Nagaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for inspecting element layout in semiconductor device
    Publication number: 20070234262
    Abstract: A method for inspecting the layout of elements included in a semiconductor device. The method includes setting paired layout inspection requirements including at least an element interval at which a paired layout is enabled, inspecting whether or not the elements that are to be inspected for paired layout satisfy the paired layout inspection requirements, setting a search area for each of the elements that are to be inspected for paired layout, and extracting figures included in the search areas of the elements that are to be inspected for paired layout and inspecting whether or not the extracted figures of the elements that are to be inspected for paired layout are congruent to each other.
    Type: Application
    Filed: September 19, 2006
    Publication date: October 4, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Masato Uedi, Mamoru Sobue, Kouhei Nagaya, Takeshi Inoue, Yoshinori Gotou