Patents by Inventor Kouichi Anno

Kouichi Anno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090322704
    Abstract: The display device with a touch panel includes: a display panel; and a touch panel formed to be overlaid on the display panel, in which: the touch panel includes X electrodes and Y electrodes which intersect the X electrodes; the X electrodes and the Y electrodes include intersection portions at which the X electrodes and the Y electrodes intersect each other, and electrode portions each formed between the intersection portions; and either the electrode portions of the X electrode or the electrode portion of the Y electrodes are smaller in area than another thereof so that a capacitance of one line of the X electrodes and a capacitance of one line of the Y electrodes are equal to each other. The display device with a touch panel has a large S/N ratio and a high detection sensitivity.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 31, 2009
    Inventor: Kouichi ANNO
  • Publication number: 20090256821
    Abstract: The electrostatic capacity coupling type touch panel includes X electrodes (XP) and Y electrodes (YP) which intersect each other via a first insulating layer, and a plurality of Z electrodes in floating states to each other via a second insulating layer. For the second insulating layer, a material which changes in thickness by pressing of touch is used. The Z electrode is disposed so as to overlap both an X electrode and a Y electrode which are adjacent to each other. In a pad part of the X electrode, an area is larger toward the center of the X electrode and an area is smaller toward the center of the adjacent X electrode. Therefore, the nonconductive input means can be used, and highly accurate position detection is realized with a small number of electrodes even when a touch area is small.
    Type: Application
    Filed: April 14, 2009
    Publication date: October 15, 2009
    Inventors: Norio Mamba, Tsutomu Furuhashi, Kouichi Anno
  • Publication number: 20090079889
    Abstract: Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.
    Type: Application
    Filed: November 17, 2008
    Publication date: March 26, 2009
    Inventors: Hitoshi Komeno, Kouichi Anno
  • Patent number: 7471349
    Abstract: Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: December 30, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Komeno, Kouichi Anno
  • Patent number: 7342626
    Abstract: The present invention prevents a frame-like luminance difference generated in a portion which surrounds a light transmissive region. In a pixel region formed on a substrate, a first pixel electrode formed of a light transmissive conductive layer is formed in one light transmissive region which is formed by partitioning the pixel region and a second pixel electrode formed of a non-light transmissive conductive film is formed on the other light reflective region. The first pixel electrode is positioned as a lower layer with respect to an insulation film. A hole is formed in the insulation film in a region corresponding to the light transmissive region so as to expose the first pixel electrode. The second pixel electrode is formed on a light reflective region of the insulation film. Light shielding is performed at a portion corresponding to a side wall surface of the hole formed in the insulation film.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: March 11, 2008
    Assignee: Hitachi Displays, Ltd.
    Inventors: Kouichi Anno, Hitoshi Komeno, Tomonori Nishino
  • Patent number: 7298430
    Abstract: The liquid crystal display device of the present invention can prevent the generation of the frame-like brightness difference at a portion which surrounds a light transmitting region. A pixel region formed over one substrate SUB1 which constitutes a liquid crystal display device includes a light transmitting region LTA which allows transmitting of light and a light reflecting region LRA which allows reflection of light. The light transmitting region LTA includes a first pixel electrode TPX formed of a conductive layer having the light transmitting property, while the light reflecting region LRA is formed of a second pixel electrode RPX formed of a conductive film having the non-light-transmitting property. A holding capacitance electrode CT which is connected to a holding capacitance line CL is formed below the second pixel electrode RPX.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: November 20, 2007
    Assignee: Hitachi Displays, Ltd.
    Inventors: Tomonori Nishino, Masayuki Hikiba, Kouichi Anno
  • Patent number: 7259817
    Abstract: The present invention is configured so that it has a first substrate, a second substrate, a liquid crystal layer pinched between the first substrate and second substrate, and a driving unit, wherein a characteristic of a reflectivity versus an applied voltage is a normally closed type and a characteristic of a transmissivity versus an applied voltage is the normally closed type: wherein the first substrate has a common electrode, and an upside polarization plate and upside phase plate on an upper surface; wherein the second substrate has a reflective electrode and transparent electrode connected with an active element, and a downside polarization plate and downside phase plate on a lower surface; wherein the liquid crystal layer has a twist angle not less than 40 degrees and not more than 65 degrees; wherein a retardation of the liquid crystal layer in a reflective display unit is within a range of not less than 230 nm and not more than 300 nm; and wherein a retardation of the liquid crystal layer in a transm
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: August 21, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Itou, Hiroko Hayata, Kouichi Anno, Shinichi Komura
  • Patent number: 7164453
    Abstract: Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: January 16, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Komeno, Kouichi Anno
  • Publication number: 20060262240
    Abstract: The present invention prevents a frame-like luminance difference generated in a portion which surrounds a light transmissive region. In a pixel region formed on a substrate, a first pixel electrode formed of a light transmissive conductive layer is formed in one light transmissive region which is formed by partitioning the pixel region and a second pixel electrode formed of a non-light transmissive conductive film is formed on the other light reflective region. The first pixel electrode is positioned as a lower layer with respect to an insulation film. A hole is formed in the insulation film in a region corresponding to the light transmissive region so as to expose the first pixel electrode. The second pixel electrode is formed on a light reflective region of the insulation film. Light shielding is performed at a portion corresponding to a side wall surface of the hole formed in the insulation film.
    Type: Application
    Filed: July 31, 2006
    Publication date: November 23, 2006
    Inventors: Kouichi Anno, Hitoshi Komeno, Tomonori Nishino
  • Patent number: 7102712
    Abstract: To respective pixel regions formed on a liquid-crystal side of one of a pair of substrates which are arranged to face each other in an opposed manner while sandwiching liquid crystal therebetween, pixel electrodes which reflect an external light incident on the pixel electrodes through the other substrate are provided. Protruding portions are formed on a surface of the pixel electrode in a scattered manner and the protruding portions have two or more kinds of shapes which are different from each other when the pixel electrodes are viewed in a plan view. The protruding portions formed on the surface of the pixel electrode are formed of island-like multi-layered material layers which are positioned at lower layer sides of the pixel electrodes. Due to such a constitution, the generation of the interference light can be suppressed.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: September 5, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Kouichi Anno, Tohru Sasaki
  • Publication number: 20060152642
    Abstract: Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.
    Type: Application
    Filed: March 15, 2006
    Publication date: July 13, 2006
    Inventors: Hitoshi Komeno, Kouichi Anno
  • Patent number: 7002658
    Abstract: Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: February 21, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Komeno, Kouichi Anno
  • Patent number: 6995812
    Abstract: The present invention provides a liquid crystal display device which can largely suppress the reduction of contrast which occurs in a light reflection mode of a liquid crystal display device. On a liquid-crystal-side surface of one of substrates which are arranged to face each other in an opposed manner while sandwiching liquid crystal therebetween, the liquid crystal display device includes pixel regions each of which is classified into a light reflection portion and a light transmission portion. On each pixel region, a first light-transmitting pixel electrode which is formed on the light reflection portion and the light transmission portion, a material layer which is formed on a major portion of the light reflection portion, an insulation layer having an opening formed at a portion corresponding to the light transmission portion, and a second pixel electrode which is formed on the light reflection portion and functions as a reflection film are sequentially laminated.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: February 7, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Kouichi Anno, Hiroko Hayata, Tohru Sasaki
  • Patent number: 6989881
    Abstract: A display device having a substrate, and a display area and a peripheral area being formed on the substrate. A signal line is extended from the display area to the peripheral area on the substrate, and the signal line at the peripheral area is covered with a first insulating film, a semiconductor layer, and a second insulating film in this order.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: January 24, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Kawamura, Takeshi Tanaka, Kikuo Ono, Masaaki Matsuda, Kouichi Anno, Hiroshi Okawara
  • Publication number: 20050231678
    Abstract: Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.
    Type: Application
    Filed: June 17, 2005
    Publication date: October 20, 2005
    Inventors: Hitoshi Komeno, Kouichi Anno
  • Publication number: 20050225709
    Abstract: Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.
    Type: Application
    Filed: June 9, 2005
    Publication date: October 13, 2005
    Inventors: Hitoshi Komeno, Kouichi Anno
  • Publication number: 20050190311
    Abstract: The present invention provides a liquid crystal display device which can largely suppress the reduction of contrast which occurs in a light reflection mode of a liquid crystal display device. On a liquid-crystal-side surface of one of substrates which are arranged to face each other in an opposed manner while sandwiching liquid crystal therebetween, the liquid crystal display device includes pixel regions each of which is classified into a light reflection portion and a light transmission portion. On each pixel region, a first light-transmitting pixel electrode which is formed on the light reflection portion and the light transmission portion, a material layer which is formed on a major portion of the light reflection portion, an insulation layer having an opening formed at a portion corresponding to the light transmission portion, and a second pixel electrode which is formed on the light reflection portion and functions as a reflection film are sequentially laminated.
    Type: Application
    Filed: April 26, 2005
    Publication date: September 1, 2005
    Inventors: Kouichi Anno, Hiroko Hayata, Tohru Sasaki
  • Patent number: 6912026
    Abstract: The present invention provides a liquid crystal display device which can largely suppress the reduction of contrast which occurs in a light reflection mode of a liquid crystal display device. On a liquid-crystal-side surface of one of substrates which are arranged to face each other in an opposed manner while sandwiching liquid crystal therebetween, the liquid crystal display device includes pixel regions each of which is classified into a light reflection portion and a light transmission portion. On each pixel region, a first light-transmitting pixel electrode which is formed on the light reflection portion and the light transmission portion, a material layer which is formed on a major portion of the light reflection portion, an insulation layer having an opening formed at a portion corresponding to the light transmission portion, and a second pixel electrode which is formed on the light reflection portion and functions as a reflection film are sequentially laminated.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: June 28, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kouichi Anno, Hiroko Hayata, Tohru Sasaki
  • Patent number: 6912036
    Abstract: Even when gate lines are pulled around at both left and right picture frame regions, it is possible to prevent a gate wiring pattern which is constituted of the gate lines and gate-line pull-around lines and a storage wiring pattern which is constituted of storage lines and a common line which connects storage lines each other from getting over each other. The gate lines GL1, GL2 are pulled around by the gate-line pull-around lines GLL1, GLL2 in both left and right picture frame regions. The common lines B2, B3 which connect the storage lines STL each other are formed at both left and right picture frame regions. Further, the gate wiring pattern which is constituted of the gate lines GL1, GL2 and the gate-line pull-around lines GLL1, GLL2 and the storage wiring pattern which is constituted of the storage lines STL and the common lines B2, B3 do not cross each other.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: June 28, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hitoshi Komeno, Kouichi Anno
  • Patent number: RE39798
    Abstract: A liquid crystal display device and a manufacturing method therefor are provided where the number of processes for manufacturing TFT substrates can be decreased and a high production yield can be attained. To attain these objects, an image signal bus-line includes at least a transparent conductive film and a semiconductor layer. A pattern of the transparent conductive film extends up to a thin film transistor to form its drain electrode, and a pattern of a semiconductor layer extends up to the transistor to form its source electrode. By virtue of these arrangements, the thin film transistor substrate can be manufactured using as little as three or four photolithography processes.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: August 28, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Kikuo Ono, Kazuhiro Ogawa, Takashi Suzuki, Kouichi Anno, Hiroki Sakuta, Makoto Tsumura, Masaaki Kitajima, Genshiro Kawachi