Abstract: A video display system comprising a plurality of video display apparatuses 11 to 13 for displaying video signals Sv being supplied as video. A specific video display apparatus 11 out of a plurality of the video display apparatuses 11 to 13 discriminates video characteristics Pv1 to Pv5 of the video signal Sv to output identification signals IDa to IDd that correspond to the discriminated video characteristics (Pa1 to Pa5) to (Pd1 to Pd5) and simultaneously displays the video signal Sv according to the display characteristic characteristics (Qa1 to Qa3) to (Qc1 to Qc3) stored in correspondence to the identification signals IDa to IDd. The other video display apparatuses 12 and 13 than the specific video display apparatus 11 display the video signals Sv according to the display characteristic characteristics (Qa1 to Qa3) to (Qc1 to Qc3) stored in correspondence to the identification signals IDa to IDd.

Abstract: A video display system comprising a plurality of video display apparatuses 11 to 13 for displaying video signals Sv being supplied as video. A specific video display apparatus 11 out of a plurality of the video display apparatuses 11 to 13 discriminates video characteristics Pv1 to Pv5 of the video signal Sv to output identification signals IDa to IDd that correspond to the discriminated video characteristics (Pa1 to Pa5) to (Pd1 to Pd5) and simultaneously displays the video signal Sv according to the display characteristic characteristics (Qa1 to Qa3) to (Qc1 to Qc3) stored in correspondence to the identification signals IDa to IDd. The other video display apparatuses 12 and 13 than the specific video display apparatus 11 display the video signals Sv according to the display characteristic characteristics (Qa1 to Qa3) to (Qc1 to Qc3) stored in correspondence to the identification signals IDa to IDd.

Abstract: A circuit for generating an image signal having an image pattern creating device for successively reading data from a memory in step with a deflection operation. The image pattern creating creates an image pattern consisting of dots, the minimum width of which is determined by the storage capacity of the memory. A compressor detects the horizontal edges of the image pattern and delays the horizontal edges by a period shorter than the period corresponding to the minimum width of the dots thereby compressing the width of the dots.

Abstract: A digital conversion circuit with a convergence deviation correcting circuit. A coefficient storing circuit stores coefficients of fundamental correction waves. By weighting these fundamental correction waves using the coefficient storing circuit, a correction data storing circuit is provided with correcting data. Controlling means controls this entire operation. Using the correction data, the convergent deviation of a scanning line of a scanning picture is corrected. By weighting each fundamental correction wave with a weighting coefficient, a synthesized wave is produced. This synthesized correction data is read from a correction data storing circuit in synchronism with deflection scanning and is supplied to a convergence deviation correcting circuit.