Abstract: A display device that includes a plurality of scanning lines, a plurality of data lines, and a pixel unit in which a pixel is specified by the scanning line and the data line, in which image data of one line is simultaneously displayed for a plurality of adjacent scanning lines, image data to be simultaneously displayed is made different between an N frame and an (N+1) frame that are temporally consecutive, and the image data is shifted by one line, and the image data of a last scanning line of at least one of the N frame or the (N+1) frame is hidden.

Abstract: Drive circuits and display devices with reduced power consumption are disclosed. In one example, a drive circuit includes a setting circuit configured to precharge, to a first voltage, a video signal line connected to a first transistor configured to sample a voltage of the video signal line, and an adjustment circuit configured to adjust a voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage during a time period corresponding to a second voltage set in the video signal line.

Abstract: The invention of the present application provides a drive circuit, a display device, and a drive method for reducing power consumption. A drive circuit of the present invention includes a setting circuit configured to precharge, to a first voltage, a video signal line connected to a first transistor configured to sample a voltage of the video signal line, and an adjustment circuit configured to adjust a voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage during a time period corresponding to a second voltage set in the video signal line.

Abstract: The invention of the present application provides a drive circuit, a display device, and a drive method for reducing power consumption. A drive circuit of the present invention includes a setting circuit configured to precharge, to a first voltage, a video signal line connected to a first transistor configured to sample a voltage of the video signal line, and an adjustment circuit configured to adjust a voltage of the video signal line by charging or discharging the video signal line precharged to the first voltage during a time period corresponding to a second voltage set in the video signal line.

Abstract: To improve display quality in a case where pixels are driven by using a ramp wave voltage.

Abstract: A display device that includes a plurality of scanning lines, a plurality of data lines, and a pixel unit in which a pixel is specified by the scanning line and the data line, in which image data of one line is simultaneously displayed for a plurality of adjacent scanning lines, image data to be simultaneously displayed is made different between an N frame and an (N+1) frame that are temporally consecutive, and the image data is shifted by one line, and the image data of a last scanning line of at least one of the N frame or the (N+1) frame is hidden.

Abstract: A display device includes: data-line pairs arranged side by side along a first direction; gate lines arranged side by side along a second direction; a display section including pixels each disposed at an intersection of a data-line pair and a gate line and connected to one or both of the data-line pair; a data-line drive circuit supplying a positive-phase data signal to one of the data-line pair and a negative-phase data signal to the other, and allowing the data-line pair to stay in a high-impedance state before writing of an image signal to the pixels; and a short circuit putting the data-line pair in a short-circuit state while the data-line pair stays in the high-impedance state, and then releasing the short-circuit state Following the release of the short-circuit state, the positive-phase data signal or/and the negative-phase data signal are written into the pixel as the image signal.

Abstract: A display device includes: data-line pairs arranged side by side along a first direction; gate lines arranged side by side along a second direction; a display section including pixels each disposed at an intersection of a data-line pair and a gate line and connected to one or both of the data-line pair; a data-line drive circuit supplying a positive-phase data signal to one of the data-line pair and a negative-phase data signal to the other, and allowing the data-line pair to stay in a high-impedance state before writing of an image signal to the pixels; and a short circuit putting the data-line pair in a short-circuit state while the data-line pair stays in the high-impedance state, and then releasing the short-circuit state Following the release of the short-circuit state, the positive-phase data signal or/and the negative-phase data signal are written into the pixel as the mage signal.

Abstract: A display device includes: data-line pairs arranged side by side along a first direction; gate lines arranged side by side along a second direction; a display section including pixels each disposed at an intersection of a data-line pair and a gate line and connected to one or both of the data-line pair; a data-line drive circuit supplying a positive-phase data signal to one of the data-line pair and a negative-phase data signal to the other, and allowing the data-line pair to stay in a high-impedance state before writing of an image signal to the pixels; and a short circuit putting the data-line pair in a short-circuit state while the data-line pair stays in the high-impedance state, and then releasing the short-circuit state Following the release of the short-circuit state, the positive-phase data signal or/and the negative-phase data signal are written into the pixel as the mage signal.

Abstract: A display device includes: data-line pairs arranged side by side along a first direction; gate lines arranged side by side along a second direction; a display section including pixels each disposed at an intersection of a data-line pair and a gate line and connected to one or both of the data-line pair; a data-line drive circuit supplying a positive-phase data signal to one of the data-line pair and a negative-phase data signal to the other, and allowing the data-line pair to stay in a high-impedance state before writing of an image signal to the pixels; and a short circuit putting the data-line pair in a short-circuit state while the data-line pair stays in the high-impedance state, and then releasing the short-circuit state Following the release of the short-circuit state, the positive-phase data signal or/and the negative-phase data signal are written into the pixel as the mage signal.