Patents by Inventor Kouichi Kanemoto

Kouichi Kanemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7552876
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: June 30, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Publication number: 20080257968
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Application
    Filed: October 25, 2007
    Publication date: October 23, 2008
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Patent number: 7303138
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: December 4, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Patent number: 7234644
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: June 26, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Publication number: 20060157572
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Application
    Filed: March 20, 2006
    Publication date: July 20, 2006
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Publication number: 20060157573
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Application
    Filed: March 20, 2006
    Publication date: July 20, 2006
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Patent number: 7055757
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: June 6, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Patent number: 7048197
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: May 23, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Patent number: 6945465
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: September 20, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Patent number: 6924547
    Abstract: A memory card is disclosed which not only suppresses a lowering of the manufacturing yield caused by warping of a semiconductor chip sealing member, but also reduces the manufacturing cost by using a less expensive material. The memory card comprises a thin plate-like cap formed of a synthetic resin and a sealing member mounted inside the cap. Inside the sealing member are sealed a metallic lead frame and three semiconductor chips (two memory chips and one control chip) mounted on part (leads) of the lead frame. The semiconductor chips are electrically connected to leads through Au wires. Connecting terminals integral with the lead frame are exposed to the back side of the sealing member.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: August 2, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Kouichi Kanemoto, Masachika Masuda
  • Publication number: 20050110127
    Abstract: A thin semiconductor device which assures a high production yield. The semiconductor device includes: first and second semiconductor chips each of which has electrodes over its first surface; first leads electrically connected with the electrodes of the first semiconductor chip through first bonding wires; second leads electrically connected with the electrodes of the second semiconductor chip through second bonding wires; a die pad with first and second surfaces opposite each other where the first semiconductor chip's first surface is bonded to the first surface and the second semiconductor chip's first surface is bonded to the second surface; and a resin sealer which seals the first and second semiconductor chips, inner portions of the first and second leads, the first and second bonding wires, and the die pad. The inner portions of the first and second leads and the die pad lie at the same height level in a thickness direction of the resin sealer.
    Type: Application
    Filed: November 5, 2004
    Publication date: May 26, 2005
    Inventors: Kouichi Kanemoto, Kazunari Suzuki, Toshihiro Shiotsuki, Hideyuki Suga
  • Publication number: 20050090128
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Application
    Filed: November 16, 2004
    Publication date: April 28, 2005
    Inventors: Hirotake Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Publication number: 20050090129
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Application
    Filed: November 16, 2004
    Publication date: April 28, 2005
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Publication number: 20040084538
    Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.
    Type: Application
    Filed: October 28, 2003
    Publication date: May 6, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Kouichi Kanemoto, Yousuke Yukawa
  • Publication number: 20030227075
    Abstract: A memory card is disclosed which not only suppresses a lowering of the manufacturing yield caused by warping of a semiconductor chip sealing member, but also reduces the manufacturing cost by using a less expensive material. The memory card comprises a thin plate-like cap formed of a synthetic resin and a sealing member mounted inside the cap. Inside the sealing member are sealed a metallic lead frame and three semiconductor chips (two memory chips and one control chip) mounted on part (leads) of the lead frame. The semiconductor chips are electrically connected to leads through Au wires. Connecting terminals integral with the lead frame are exposed to the back side of the sealing member.
    Type: Application
    Filed: May 23, 2003
    Publication date: December 11, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Kouichi Kanemoto, Masachika Masuda
  • Publication number: 20030151134
    Abstract: A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.
    Type: Application
    Filed: December 31, 2002
    Publication date: August 14, 2003
    Inventors: Hirotaka Nishizawa, Masachika Masuda, Kouichi Kanemoto, Tamaki Wada
  • Patent number: 6531773
    Abstract: A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside of the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: March 11, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hirotaka Nishizawa, Masachika Masuda, Kouichi Kanemoto, Tamaki Wada
  • Patent number: 6501173
    Abstract: A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: December 31, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hirotaka Nishizawa, Masachika Masuda, Kouichi Kanemoto, Tamaki Wada
  • Patent number: 6501183
    Abstract: A first semiconductor chip (2) is bonded and secured to a second semiconductor chip (3) with a back surface of the first semiconductor chip (2) and a circuit forming surface (3X) of the second semiconductor chip (3) facing each other, and an inner portion of a support lead (6) is bonded and secured to the circuit forming surface (3X) of the second semiconductor chip (3). Such a configuration makes it possible to provide a semiconductor with a reduced thickness.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: December 31, 2002
    Assignees: Hitachi, Ltd., Hitachi USLI Systems Co., Ltd.
    Inventors: Kouichi Kanemoto, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Mikako Kimura
  • Patent number: 6492727
    Abstract: A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside of the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: December 10, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hirotaka Nishizawa, Masachika Masuda, Kouichi Kanemoto, Tamaki Wada