Patents by Inventor Kouichi Muraoka

Kouichi Muraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8227356
    Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: July 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kouichi Muraoka
  • Publication number: 20120058645
    Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.
    Type: Application
    Filed: August 26, 2011
    Publication date: March 8, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kouichi MURAOKA
  • Patent number: 8021988
    Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kouichi Muraoka
  • Patent number: 7749919
    Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu Sakuma, Daisuke Matsushita, Koichi Kato, Yasushi Nakasaki, Izumi Hirano, Kouichi Muraoka, Yuichiro Mitani, Shigeto Fukatsu, Toshihide Ito
  • Patent number: 7737511
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: June 15, 2010
    Assignee: Kabushikik Kaisha Toshiba
    Inventors: Kouichi Muraoka, Kazuaki Kurihara
  • Patent number: 7655971
    Abstract: A nonvolatile semiconductor memory device includes: a source region and a drain region formed at a distance from each other in a semiconductor substrate; a tunnel insulating film formed on the semiconductor substrate between the source region and the drain region; a charge storage film formed on the tunnel insulating film; a first alumina layer formed on the charge storage film, and having a first impurity element added thereto, the first impurity element having an octacoordinate ion radius of 63 pm or greater, the first impurity element having a concentration distribution in a layer thickness direction of the first alumina layer that becomes the largest in a region close to the side of the charge storage film; a second alumina layer formed on the first alumina layer, and not having the first impurity element added thereto; and a control gate electrode formed on the second alumina layer.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: February 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro Ino, Kouichi Muraoka
  • Publication number: 20080299781
    Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.
    Type: Application
    Filed: April 21, 2008
    Publication date: December 4, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kouichi Muraoka
  • Publication number: 20080217706
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.
    Type: Application
    Filed: May 16, 2008
    Publication date: September 11, 2008
    Inventors: Kouichi MURAOKA, Kazuaki Kurihara
  • Patent number: 7422953
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: September 9, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Muraoka, Kazuaki Kurihara
  • Publication number: 20080211011
    Abstract: It is made possible to provide a nonvolatile semiconductor memory element that can be miniaturized and can store multi-level data. A nonvolatile semiconductor memory element includes a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; and a gate structure formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region. The gate structure includes a tunnel insulating layer, a resistance variable layer formed above the tunnel insulating layer and made of a metal oxide, and a first electrode formed on the resistance variable layer.
    Type: Application
    Filed: February 1, 2008
    Publication date: September 4, 2008
    Inventors: Akira TAKASHIMA, Kouichi Muraoka
  • Publication number: 20080173930
    Abstract: The present invention provides a semiconductor memory device having a tunnel insulating film that does not degrade the endurance characteristics when writing/erasing is repeated, even if the tunnel insulating film is made thinner. The semiconductor memory device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate, and including a silicon oxynitride film and a silicon-rich silicon oxide film formed on the silicon oxynitride film, the silicon oxynitride film having a stacked structure formed with a first silicon oxynitride layer, a silicon nitride layer, and a second silicon oxynitride layer in order; a charge storage layer formed on the first insulating film; a second insulating film formed on the charge storage layer; and a control gate formed on the second insulating film.
    Type: Application
    Filed: September 19, 2007
    Publication date: July 24, 2008
    Inventors: Hiroshi Watanabe, Daisuke Matsushita, Kouichi Muraoka, Yasushi Nakasaki, Koichi Kato
  • Publication number: 20080173927
    Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.
    Type: Application
    Filed: September 6, 2007
    Publication date: July 24, 2008
    Inventors: Kiwamu Sakuma, Daisuke Matsushita, Koichi Kato, Yasushi Nakasaki, Izumi Hirano, Kouichi Muraoka, Yuichiro Mitani, Shigeto Fukatsu, Toshihide Ito
  • Patent number: 7385264
    Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 10, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kouichi Muraoka
  • Publication number: 20080116507
    Abstract: A nonvolatile semiconductor memory device includes: a source region and a drain region formed at a distance from each other in a semiconductor substrate; a tunnel insulating film formed on the semiconductor substrate between the source region and the drain region; a charge storage film formed on the tunnel insulating film; a first alumina layer formed on the charge storage film, and having a first impurity element added thereto, the first impurity element having an octacoordinate ion radius of 63 pm or greater, the first impurity element having a concentration distribution in a layer thickness direction of the first alumina layer that becomes the largest in a region close to the side of the charge storage film; a second alumina layer formed on the first alumina layer, and not having the first impurity element added thereto; and a control gate electrode formed on the second alumina layer.
    Type: Application
    Filed: September 19, 2007
    Publication date: May 22, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro INO, Kouichi Muraoka
  • Publication number: 20050280069
    Abstract: A semiconductor device using a high dielectric constant insulator having reduced leak current as an interelectrode insulator is provided by comprising a first insulator formed on a semiconductor substrate, a first gate electrode formed on the first insulator, a second gate electrode formed above the first gate electrode, and a second crystallized insulator formed between the first gate electrode and the second gate electrode.
    Type: Application
    Filed: August 24, 2004
    Publication date: December 22, 2005
    Inventors: Ichiro Mizushima, Tetsuya Kai, Yoshio Ozawa, Kouichi Muraoka, Shinichi Nakamura
  • Publication number: 20040214400
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.
    Type: Application
    Filed: May 17, 2004
    Publication date: October 28, 2004
    Inventors: Kouichi Muraoka, Kazuaki Kurihara
  • Patent number: 6800519
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: October 5, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Muraoka, Kazuaki Kurihara
  • Publication number: 20040018690
    Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.
    Type: Application
    Filed: March 31, 2003
    Publication date: January 29, 2004
    Applicant: Kabushi Kaisha Toshiba
    Inventor: Kouichi Muraoka
  • Publication number: 20030057504
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.
    Type: Application
    Filed: September 12, 2002
    Publication date: March 27, 2003
    Inventors: Kouichi Muraoka, Kazuaki Kurihara
  • Patent number: 6165916
    Abstract: The present invention provides a method of forming a film, having the step of allowing a first chemical substance to be adsorbed on a surface of a silicon substrate by a gaseous phase method, and the step of introducing a gas containing a second chemical substance onto the substrate surface having the first chemical substance adsorbed thereon for forming a silicon compound layer on the silicon substrate, the silicon compound layer consisting essentially of a silicon compound formed by a reaction between the first chemical substance adsorbed on the substrate surface and the second chemical substance.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: December 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Muraoka, Hitoshi Itoh