Abstract: A reversely-rotatable roller conveys a sheet having an image formed on its one side at a sheet conveying velocity faster than that of a conveying roller by normal rotation and then, the reversely-rotatable roller conveys the sheet to a re-conveying path by reverse rotation. The sheet conveying velocity of the reversely-rotatable roller when the reversely-rotatable roller reversely rotates is made slower than the sheet conveying velocity when the reversely-rotatable roller normally rotates so that the sheet conveying velocity of the re-conveying roller is substantially equal to or slower than the sheet conveying velocity of the conveying roller.

Abstract: A first switch receives an input signal. A second switch receives the input signal, in parallel with the first switch. An output potential sensing inverter detects the potential of an output signal derived from a connection point of the first switch and the second switch. Upon receipt of an output of the output potential sensing inverter, an input switch controls whether the input signal is inputted to the second switch or not. When the potential of the output signal exceeds a predetermined threshold voltage, the output potential sensing inverter performs control such that the input switch be turned off.

Abstract: A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

Abstract: A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.

Abstract: A memory includes conductive layers provided to extend along the word lines, memory cells each including a diode having a cathode connected to the conductive layer and a source line reading data stored in the memory cells, wherein either the conductive layers or the bit lines are in floating states in a standby time.

Abstract: A memory allowing reduction of a memory cell size is obtained. This memory comprises a first conductive type first impurity region formed on the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a word line, a plurality of second conductive type second impurity regions formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode, a bit line formed on the semiconductor substrate and connected to the second impurity regions and a wire provided above the bit line and connected to the first impurity region every prescribed interval.

Abstract: A first switch (M1) receives an input signal. A second switch (M2) receives an input signal in parallel with the first switch (M1). An output potential detection inverter (30) detects a potential of an output signal obtained from a connection point between the first switch (M1) and the second switch (M2). An input switch (M3) receives an output of the output potential detection inverter (30) and controls whether to supply an input signal to the second switch (M2). The output potential detection inverter (30) controls to turn OFF the input switch (M3) if the output signal potential exceeds a predetermined threshold voltage.

Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.

Abstract: In a double edge triggered flip-flop circuit, a first latch circuit latches input data at either one of rising edge and falling edge of clock signal. A second latch circuit, which is provided in parallel with the first latch circuit, latches the input data at the other of the either one of rising edge and falling edge of the clock signal. At least one of the first latch circuit and the second latch circuit is configured by an SRAM (Static Random Access Memory) type.

Abstract: A memory wherein any “disturb effect” can be suppressed in which data in unselected memory cells are lost. This memory has a memory cell array (1) including bit lines, word lines, which are disposed to intersect the bit lines, and memory cells (12) each connected between bit and word lines. In this memory, an access operation, which includes at least one of read, rewrite and write operations, is made to a selected memory cell (12). During this access operation, it is performed to apply to the memory cell (12) a first voltage pulse, which provides an electrical field in a first direction so as to invert a stored data, and a second voltage pulse, which provides as electrical field in the opposite direction to the first one so as not to invert the stored data. In addition, a recovery operation for recovering a residual polarization amount is made to the memory cell (12).

Abstract: A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

Abstract: An ejector for a fuel cell system of the present invention includes a nozzle having a nozzle hole for discharging hydrogen supplied via an inlet port of an ejector body, a diffuser for mixing hydrogen discharged from the nozzle hole and hydrogen off-gas discharged and returned via a circulation passage from a fuel cell, a needle displacing in the axial direction by a driving force of a solenoid, and a bearing member held in a hollow portion of the nozzle, and having a through hole that movably supports the needle in the axial direction.

Abstract: A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

Abstract: A floating gate made of polysilicon is provided on a semiconductor substrate through the medium of a gate insulator. A side-wall insulating film is provided on each side wall of the floating gate. A first impurity diffusion layer, which occupies a space within the semiconductor substrate, is provided separately apart from the floating gate by a predetermined distance. A second impurity diffusion layer, which occupies a space within the semiconductor substrate, overlaps with the floating gate. Electrons are injected into the floating gate by applying a high voltage to the second impurity diffusion layer in capacitive coupling with the floating gate.

Abstract: A memory is so formed that, in a first block and a second block each including a prescribed number of the bit lines arranged therein, positions of the bit lines simultaneously selected in the first and second blocks with reference to ends of the first and second blocks respectively are different from each other.

Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a plurality of memory cells including diodes, a plurality of bit lines and a first conductive type first impurity region arranged to intersect with the bit lines for functioning as first electrodes of the diodes included in the memory cells and a word line. The first impurity region is divided every bit line group formed by a prescribed number of bit lines along a direction intersecting with the extensional direction of the first impurity region.

Abstract: A memory includes a plurality of word lines, a plurality of bit lines so arranged as to intersect with the plurality of word lines, a plurality of memory cells arranged on positions where the word lines and the bit lines intersect with each other respectively and selection circuits connected to the bit lines, wherein the current driving ability of the selection circuits is different depending on positions where the bit lines are arranged.

Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.

Abstract: A semiconductor device capable of improving the accuracy determines whether a prescribed input potential is higher or lower than a reference potential. This semiconductor device comprises first capacitance unit and second capacitance unit having different ON- and OFF-state capacitances. The semiconductor device changes the potential of a first electrode of the first capacitance unit and the potential of a first electrode of the second capacitance unit from a first potential to a second potential thereby enlarging the difference between a potential input in a second electrode of the first capacitance unit and a potential input in a second electrode of the second capacitance unit and comparing the potential input in the second electrode of the first capacitance unit and the potential input in the second electrode of the second capacitance unit with each other.

Abstract: A memory capable of reducing the memory cell size is provided. This memory includes a first conductive type first impurity region formed on a memory cell array region of the main surface of a semiconductor substrate for functioning as a first electrode of a diode included in a memory cell and a plurality of second conductive type second impurity regions, formed on the surface of the first impurity region at a prescribed interval, each functioning as a second electrode of the diode.