Patents by Inventor Kouichirou Adachi

Kouichirou Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8698193
    Abstract: The light emitting device of the invention includes a first electrode, a second electrode, and a carrier formed between the first electrode and the second electrode and containing germanium light emitters, wherein the germanium light emitters contain germanium oxide in which at least part of the germanium oxide has oxygen deficiency and have a wavelength peak of emission in both or either the range of 250 to 350 nm and/or the range of 350 to 500 nm when a potential difference is applied to the first electrode and the second electrode.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: April 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobutoshi Arai, Masatomi Harada, Kouichirou Adachi, Hiroshi Iwata
  • Publication number: 20100026198
    Abstract: The light emitting device of the invention includes a first electrode, a second electrode, and a carrier formed between the first electrode and the second electrode and containing germanium light emitters, wherein the germanium light emitters contain germanium oxide in which at least part of the germanium oxide has oxygen deficiency and have a wavelength peak of emission in both or either the range of 250 to 350 nm and/or the range of 350 to 500 nm when a potential difference is applied to the first electrode and the second electrode.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 4, 2010
    Inventors: Nobutoshi ARAI, Masatomi Harada, Kouichirou Adachi, Hiroshi Iwata
  • Patent number: 7312499
    Abstract: A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: December 25, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Takayuki Ogura, Akihide Shibata, Kouichirou Adachi
  • Patent number: 7129539
    Abstract: A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: October 31, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Takayuki Ogura, Akihide Shibata, Kouichirou Adachi
  • Publication number: 20060208312
    Abstract: A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.
    Type: Application
    Filed: May 1, 2006
    Publication date: September 21, 2006
    Inventors: Hiroshi Iwata, Takayuki Ogura, Akihide Shibata, Kouichirou Adachi
  • Patent number: 7074676
    Abstract: A memory film operable at a low voltage and a method of manufacturing the memory film; the method, comprising the steps of forming a first insulation film (112) on a semiconductor substrate (111) forming a first electrode, forming a first conductor film (113) on the first insulation film (112), forming a second insulation film (112B) on the surface of the first conductor film (113), forming a third insulation film containing conductor particulates (114, 115) on the second insulation film (112B), and forming a second conductor film forming a second electrode on the third insulation film.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: July 11, 2006
    Assignees: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Akihide Shibata, Nobutoshi Arai, Takayuki Ogura, Kouichirou Adachi, Seizo Kakimoto, Yukio Yasuda, Shigeaki Zaima, Akira Sakai
  • Publication number: 20050157529
    Abstract: An IC card includes a data memory portion (503) having a plurality of storage devices. The data storage devices each has: a semiconductor substrate, a well region provided in a semiconductor substrate, or a semiconductor film disposed on an insulator; a gate insulating film formed on the semiconductor substrate, the well region provided in the semiconductor substrate, or the semiconductor film disposed on the insulator; a single gate electrode formed on the gate insulating film; two memory function parts formed on opposite sides of the single gate electrode; a channel region disposed under the single gate electrode; and diffusion layer regions disposed on both sides of the channel region. Incorporating a memory using the storage devices, which allow further miniaturization, provides an IC card at low cost.
    Type: Application
    Filed: May 29, 2003
    Publication date: July 21, 2005
    Inventors: Hiroshi Iwata, Akihide Shibata, Kouichirou Adachi
  • Publication number: 20040262665
    Abstract: A semiconductor storage device comprises memory function bodies that are formed on sidewalls of gate electrode located on one side and the other side of source/drain diffusion regions and have a function to retain electric charge or polarization. A quantity of electric charge flowing in a channel region changes depending on an amount of an electric charge or polarization retained in the memory function body specified by selecting a prescribed word line and a first bit line and a second bit line.
    Type: Application
    Filed: May 18, 2004
    Publication date: December 30, 2004
    Inventors: Hiroshi Iwata, Kouichirou Adachi, Akihide Shibata
  • Publication number: 20040264270
    Abstract: A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.
    Type: Application
    Filed: May 13, 2004
    Publication date: December 30, 2004
    Inventors: Hiroshi Iwata, Takayuki Ogura, Akihide Shibata, Kouichirou Adachi
  • Publication number: 20040115883
    Abstract: A memory film operable at a low voltage and a method of manufacturing the memory film; the method, comprising the steps of forming a first insulation film (112) on a semiconductor substrate (111) forming a first electrode, forming a first conductor film (113) on the first insulation film (112), forming a second insulation film (112B) on the surface of the first conductor film (113), forming a third insulation film containing conductor particulates (114, 115) on the second insulation film (112B), and forming a second conductor film forming a second electrode on the third insulation film.
    Type: Application
    Filed: February 6, 2004
    Publication date: June 17, 2004
    Inventors: Hiroshi Iwata, Akihide Shibata, Nobutoshi Arai, Takayuki Ogura, Kouichirou Adachi, Seizo Kakimoto, Yukio Yasuda, Shigeaki Zaima, Akira Sakai
  • Patent number: 6297114
    Abstract: A semiconductor device having a gate electrode on a Si-substrate through a gate oxide film; a first impurity diffusion region having a conductivity type reversed to a well which will form a part of source and drain regions in the two opposing sides of the gate electrode through gate electrode sidewall dielectric films; a second impurity diffusion region having the same conductivity type as the first impurity diffusion region beneath the gate electrode sidewall dielectric film, touching a channel region directly below the gate electrode and being shallower than the first impurity diffusion region; a titanium silicide film on the gate electrode and the surface of the Si-substrate of the first impurity diffusion region in the two opposing sides of the gate electrode sidewall dielectric film; and a third impurity diffusion region, formed in the first impurity diffusion region, having a higher concentration than the first impurity diffusion region and the same conductivity type as the first and second impurity dif
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: October 2, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Masayuki Nakano, Seizo Kakimoto, Kouichirou Adachi, Satoshi Morishita