Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A process for producing a printed wiring board, particularly an interposer for a chip size package, which comprises the steps of (1) forming an outer insulator layer 22 having outer via-holes 24 on a substrate 32, (2) forming conducting passages 31 through the outer via-holes 24 by plating with metal up to substantially the same level as the upper surface of the outer insulator layer 22, (3) forming a thin metal film 29 on the outer insulator layer 22 and on the conducting passages 31, (4) forming a conductor layer 21 in a prescribed circuit pattern on the thin metal film 29 by plating, (5) removing the part of the thin metal film 29 on which the conductor layer 21 is not formed, (6) forming an inner insulator layer 23 on the conductor layer 21, and (7) removing the substrate 32. The outer insulator layer is formed with flatness to secure good adhesion to a semiconductor chip.

Abstract: A user uses part data forming means 101 and module data forming means 102 to input the actual dimension, physical constants and mesh dividing number for fundamental shapes which are registered in advance, thereby forming parts, and then indicates the relative position between the parts to form the entire shape of an assembly of plural parts without paying attention to coincidence or non-coincidence of nodal points. Data converting means 104 divides the shape of each part thus assembled according to the indicated mesh divisional number to generate element data and nodal point data. Further, it generates a constraint equation for connecting nodal points which are non-connected between neighboring parts, and forms an analysis model 401. A finite element method analyzer 105 uses approximate calculation means 106 to approximate a non-connected nodal point displacement from a nodal point displacement of neighboring structural elements on the basis of the constraint equation.

Abstract: There is provided a function element including a resin layer formed on a surface thereof, the resin layer having adhesive property and sealing property, the resin layer having such a pattern that a resin layer does not exist in at least one of following areas: (a) a first area around an area where device performances are influenced by resin of which the resin layer was composed, (b) a second area around pads or bumps, (c) a third area around an area on which a wiring of a substrate will exist when the function element is coupled to the substrate, and (d) a fourth area around an area on which a passive element mounted on a substrate will exist when the function element is coupled to the substrate. The function element prevents extra resin from adhering to an area of the function element where device performances will be influenced by the resin, when the function element is coupled to a substrate with a resin layer being sandwiched therebetween.