Patents by Inventor Kouji Matsuo
Kouji Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190096900Abstract: A memory device according to an embodiment includes: a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films; a first electrode provided above the stacked film; a second electrode provided above the stacked film; a plurality of first conductive pillars penetrating through the stacked film and having one end electrically connected to the first electrode and another end not connected and positioned below the stacked film; a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films; a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode; a peripheral circuit board provided above the first electrode and the second electrode; a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode; a fourth electrode provType: ApplicationFiled: March 21, 2018Publication date: March 28, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Kouji MATSUO
-
Patent number: 10211166Abstract: According to one embodiment, a semiconductor device includes a first semiconductor circuit layer including a first conductive layer, a second semiconductor circuit layer including a second conductive layer, and a third semiconductor circuit layer between the first semiconductor circuit layer and the second semiconductor circuit layer, the third semiconductor circuit layer including a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer in contact with the third conductive layer and electrically connected to the fourth conductive layer. The fifth conductive layer has a width that is narrower than a width of the third conductive layer.Type: GrantFiled: September 5, 2017Date of Patent: February 19, 2019Assignee: Toshiba Memory CorporationInventor: Kouji Matsuo
-
Publication number: 20180277497Abstract: According to one embodiment, a semiconductor device includes a first semiconductor circuit layer including a first conductive layer, a second semiconductor circuit layer including a second conductive layer, and a third semiconductor circuit layer between the first semiconductor circuit layer and the second semiconductor circuit layer, the third semiconductor circuit layer including a third conductive layer in contact with the first conductive layer, a fourth conductive layer in contact with the second conductive layer, and a fifth conductive layer in contact with the third conductive layer and electrically connected to the fourth conductive layer. The fifth conductive layer has a width that is narrower than a width of the third conductive layer.Type: ApplicationFiled: September 5, 2017Publication date: September 27, 2018Inventor: Kouji MATSUO
-
Publication number: 20180277597Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer. The storage device further includes a first variable resistance layer provided between the first and fifth conductive layers, a second variable resistance layer provided between the second and fifth conductive layers, a third variable resistance layer provided between the third and fifth conductive layers, and a fourth variable resistance layer provided between the first and sixth conductive layers. A first distance between the first and second variable resistance layers is shorter than a second distance between a portion of the first conductive layer and a portion of the second conductive layer which face each other across a region between the fifth and sixth conductive layers.Type: ApplicationFiled: September 6, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yusuke ARAYASHIKI, Kouji MATSUO
-
Patent number: 10083979Abstract: A semiconductor device includes a substrate, a semiconductor layer, first electrodes, data storage regions, first conductive regions, contacts and second conductive regions. The first electrodes are formed in the semiconductor layer arrayed in a first direction and a second direction and penetrating the insulator films and the semiconductor films in a third direction. The data storage regions are provided between each of the semiconductor films and each of the first electrodes. The first conductive regions are provided at one end of each of the semiconductor films in the first direction. The contacts are connected to one end of one of the first conductive regions in the second direction, and connection parts between each of the contacts and the first conductive regions are formed stepwise along the second direction. The second conductive regions are provided at the other end of the semiconductor layer in the first direction.Type: GrantFiled: March 17, 2017Date of Patent: September 25, 2018Assignee: Toshiba Memory CorporationInventor: Kouji Matsuo
-
Publication number: 20180083026Abstract: A semiconductor device includes a substrate, a semiconductor layer, first electrodes, data storage regions, first conductive regions, contacts and second conductive regions. The first electrodes are formed in the semiconductor layer arrayed in a first direction and a second direction and penetrating the insulator films and the semiconductor films in a third direction. The data storage regions are provided between each of the semiconductor films and each of the first electrodes. The first conductive regions are provided at one end of each of the semiconductor films in the first direction. The contacts are connected to one end of one of the first conductive regions in the second direction, and connection parts between each of the contacts and the first conductive regions are formed stepwise along the second direction. The second conductive regions are provided at the other end of the semiconductor layer in the first direction.Type: ApplicationFiled: March 17, 2017Publication date: March 22, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventor: Kouji MATSUO
-
Patent number: 9793293Abstract: A semiconductor device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed; a columnar portion provided in the stacked body and extending in a stacking direction of the electrode layers; and a first separation region provided in the stacked body and extending in a first direction. The stacked body includes a memory cell array and a staircase portion arranged in the first direction, the memory cell array including memory cells provided along the columnar portion, and the staircase portion including a plurality of terraces arranged along the first direction. The first separation region includes a first portion and a second portion in the staircase portion, the first portion having a first width in a second direction crossing the first direction, and the second portion having a second width in the second direction. The second width is narrower than the first width.Type: GrantFiled: March 17, 2017Date of Patent: October 17, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kosuke Horibe, Shinichi Nakao, Yasuhito Yoshimizu, Kouji Matsuo, Kei Watanabe, Atsuko Sakata
-
Patent number: 9153779Abstract: According to one embodiment, a memory element includes: a first electrode layer; a second electrode layer; and a memory layer provided between the first electrode layer and the second electrode layer, and the memory layer including a plurality of first oxide layers in a second oxide layer, a resistivity of each of the plurality of first oxide layers being higher than a resistivity of the second oxide layer.Type: GrantFiled: September 10, 2013Date of Patent: October 6, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tomotaka Ariga, Junichi Wada, Kouji Matsuo, Noritake Oomachi, Yoshio Ozawa
-
Patent number: 9087770Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction crossing the first direction, and a memory element provided between the first interconnect and the second interconnect at a portion where the first interconnect crosses the second interconnect. The memory element includes a variable resistance film and a stress generating film stacked with the variable resistance film to apply stress to the variable resistance film in a surface direction.Type: GrantFiled: September 10, 2013Date of Patent: July 21, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Kouji Matsuo
-
Patent number: 9040950Abstract: According to one embodiment, a nonvolatile memory device includes a first interconnect, an insulating layer, a needle-like metal oxide, and a second interconnect. The insulating layer is provided on the first interconnect. The needle-like metal oxide pierces the insulating layer in a vertical direction. The second interconnect is provided on the insulating layer.Type: GrantFiled: September 6, 2011Date of Patent: May 26, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Kouji Matsuo
-
Patent number: 9006697Abstract: A resistance change element includes a first conductive layer, a second conductive layer, and a memory layer. The memory layer is provided between the first conductive layer and the second conductive layer. The memory layer is capable of reversibly transitioning between a first state and a second state due to at least one of a voltage and a current supplied via the first conductive layer and the second conductive layer. A resistance of the second state is higher than a resistance of the first state. The memory layer includes niobium oxide. One of a (100) plane, a (010) plane, and a (110) plane of the memory layer is oriented in a stacking direction from the first conductive layer toward the second conductive layer.Type: GrantFiled: February 28, 2013Date of Patent: April 14, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Noritake Oomachi, Junichi Wada, Kouji Matsuo, Tomotaka Ariga, Yoshio Ozawa
-
Publication number: 20140284542Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction crossing the first direction, and a memory element provided between the first interconnect and the second interconnect at a portion where the first interconnect crosses the second interconnect. The memory element includes a variable resistance film and a stress generating film stacked with the variable resistance film to apply stress to the variable resistance film in a surface direction.Type: ApplicationFiled: September 10, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Kouji MATSUO
-
Publication number: 20140284546Abstract: According to one embodiment, a memory element includes: a first electrode layer; a second electrode layer; and a memory layer provided between the first electrode layer and the second electrode layer, and the memory layer including a plurality of first oxide layers in a second oxide layer, a resistivity of each of the plurality of first oxide layers being higher than a resistivity of the second oxide layer.Type: ApplicationFiled: September 10, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomotaka ARIGA, Junichi WADA, Kouji MATSUO, Noritake OOMACHI, Yoshio OZAWA
-
Patent number: 8668385Abstract: A sensor (101) is configured such that a seal member (71) is provided in a deformed manner through crimping of a portion of a tube (11) located toward a rear end (17c) of the tube (11). The seal member (71) is deformed such that a frontward-oriented surface (75), which is a bottom surface of a recess (74) formed in a front end (73) of the seal member (72), presses a rear end (45) of an insulation sheath (41) frontward. Consequently, a front end (21a) of a sensor element is pressed against a front end (12) of the tube (11) via the insulation sheath (41). By virtue of a pressing action induced by rubber-like elasticity, high sensor responsiveness is maintained over a long period of time.Type: GrantFiled: July 20, 2011Date of Patent: March 11, 2014Assignee: NGK Spark Plug Co., Ltd.Inventors: Kouji Matsuo, Satoshi Ishikawa, Masamichi Ito, Satoshi Mogari
-
Patent number: 8633535Abstract: According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.Type: GrantFiled: June 9, 2011Date of Patent: January 21, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kouji Matsuo, Toshiyuki Enda, Nobutoshi Aoki, Toshihiko Iinuma
-
Publication number: 20130341706Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor laminated film comprising an embedded insulating film, and an SOI layer laminated on a semiconductor substrate. On the embedded insulating film, multiple pillar-shaped gate electrodes embedded in the SOI layer are provided. On the SOI layer, a pillar-shaped gate insulating film is provided to surround the side surface of each of the pillar-shaped gate electrodes. On the SOI layer, multiple first bit lines are arranged. On the pillar-shaped gate electrodes, multiple word lines are arranged. In the word line direction, the adjacent pillar-shaped gate electrodes are electrically connected to each other, and, in a first bit line direction, the adjacent pillar-shaped gate electrodes are electrically insulated from each other.Type: ApplicationFiled: February 27, 2013Publication date: December 26, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Kouji MATSUO
-
Publication number: 20130248808Abstract: A resistance change element includes a first conductive layer, a second conductive layer, and a memory layer. The memory layer is provided between the first conductive layer and the second conductive layer. The memory layer is capable of reversibly transitioning between a first state and a second state due to at least one of a voltage and a current supplied via the first conductive layer and the second conductive layer. A resistance of the second state is higher than a resistance of the first state. The memory layer includes niobium oxide. One of a (100) plane, a (010) plane, and a (110) plane of the memory layer is oriented in a stacking direction from the first conductive layer toward the second conductive layer.Type: ApplicationFiled: February 28, 2013Publication date: September 26, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Noritake OOMACHI, Junichi WADA, Kouji MATSUO, Tomotaka ARIGA, Yoshio OZAWA
-
Patent number: 8486828Abstract: A semiconductor device manufacturing method has forming a metal film containing platinum by depositing a metal on a source/drain diffusion layer primarily made of silicon formed on a semiconductor substrate and on a device isolation insulating film; forming a silicide film by silicidation of an upper part of the source/drain diffusion layer by causing a reaction between silicon in the source/drain diffusion layer and the metal on the source/drain diffusion layer by a first heating processing; forming a metal oxide film by a oxidation processing to oxidize selectively at least a surface of the metal film on the device isolation insulating film; increasing the concentration of silicon in the silicide film by a second heating processing; and selectively removing the metal oxide film and an unreacted part of the metal film on the device isolation insulating film.Type: GrantFiled: May 11, 2011Date of Patent: July 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kouji Matsuo, Kazuhiko Nakamura
-
Publication number: 20120292587Abstract: According to one embodiment, a nonvolatile memory device includes a memory cell. The memory cell includes a stacked film structure. The stacked film structure is capable of maintaining a first state or a second state. The first state includes a lower electrode film, a first memory element film provided on the lower electrode film and containing a first oxide and an upper electrode film provided on the first memory element film. The second state includes the lower electrode film, the first memory element film provided on the lower electrode film, a second memory element film provided on the first memory element film and containing a second oxide and the upper electrode film provided on the second memory element film.Type: ApplicationFiled: March 20, 2012Publication date: November 22, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kouji MATSUO, Noritake OHMACHI, Tomotaka ARIGA, Junichi WADA, Yoshio OZAWA
-
Patent number: 8236641Abstract: A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.Type: GrantFiled: June 24, 2011Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Kyoichi Suguro, Kouji Matsuo