Patents by Inventor Kouji Miki

Kouji Miki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9110140
    Abstract: A semiconductor device includes: a combination circuit; and a scan circuit, wherein the scan circuit includes: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series. The first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: August 18, 2015
    Assignee: SOCIONEXT INC.
    Inventor: Kouji Miki
  • Publication number: 20140201582
    Abstract: A semiconductor device includes: a combination circuit; and a scan circuit, wherein the scan circuit includes: a first scan chain in which a plurality of first flip-flops are connected in series; and a second scan chain in which a plurality of second flip-flops are connected in series. The first scan chain is configured to capture first output data of at least one of the first flip-flops of the second scan chain, and the second scan chain is configured to capture second output data of at least one of the second flip-flops of the first scan chain.
    Type: Application
    Filed: November 5, 2013
    Publication date: July 17, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kouji MIKI
  • Patent number: 5754061
    Abstract: A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: May 19, 1998
    Assignee: Fujitsu Limited
    Inventors: Shinzou Satou, Kou Ebihara, Akiyoshi Suzuki, Keisuke Ishiwata, Kouji Miki, Hitoshi Ohmichi, Tamio Miyamura, Masamichi Kamiyama