Abstract: In order to compatibly implement improvement in withstand voltage and ON-state resistance as well as reduction in turnon loss and improvement in di/dt resistance, an n buffer layer (12) is locally exposed on a lower surface of a semiconductor substrate (160), while a polysilicon additional resistive layer (104) is formed to cover the exposed surface. An anode electrode (101) covering the lower surface of the semiconductor substrate (160) is connected to a p emitter layer (11) and the additional resistive layer (104). Thus, the n buffer layer (12) and the anode electrode (101) are connected with each other through the additional resistive layer (104), whereby a gate trigger current is reduced. Thus, turnon loss is reduced and di/dt resistance is increased. At the same time, the withstand voltage and the ON-state resistance are excellent due to provision of the n buffer layer (12).

Abstract: There is disclosed a semiconductor device wherein a p layer (7) is formed in an isolating portion (Z) and portions (1a, 1b) of an n-type base layer (1) lie on opposite sides of the p layer (7), the upper surfaces of the p layer (7) and the portions (1a, 1b) lying in the same plane as the upper surface of a p layer (3). The presence of the p layer (7) provides for high resistance to breakdown and high formation accuracy of the p layers (2, 3, 7) as compared with a structure in which the isolating portion (Z) lies in the bottom of a the recess, whereby the semiconductor device is less susceptible to short-circuit between the p-type base layer (2) and the p layer (3).