Patents by Inventor Kouji Tanaka

Kouji Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8101195
    Abstract: Provided is an artificial lymph node that is persistently effective in cancer treatment in vivo.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: January 24, 2012
    Assignee: RIKEN
    Inventors: Takeshi Watanabe, Kouji Tanaka
  • Patent number: 7994614
    Abstract: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kouji Tanaka, Seiya Isozaki
  • Patent number: 7944021
    Abstract: A semiconductor device includes an element isolation film formed on a semiconductor substrate surface of one conductivity type, a gate electrode having one pair of end portions located on a boundary between an element isolation film and an element forming region, a source region and a drain region of a reverse conductivity type arranged to sandwich a region immediately below a gate electrode, and an impurity diffusion region of the one conductivity type formed in the element forming region. The source region is separated from a region on a boundary side between the element isolation film and the element forming region in the region immediately below the gate electrode in the element forming region. In the impurity diffusion region, a portion adjacent to the region on the boundary side is arranged between the source region and the element isolation film, and is in contact with the source region and the region on the boundary side.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: May 17, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Kouji Tanaka
  • Publication number: 20110000533
    Abstract: It is possible to reduce the contact resistance so as to improve the conversion efficiency of a photoelectric conversion element structure. Provided is a photoelectric conversion element structure of the pin structure which selects an upper limit energy level of the valence band of the p-type semiconductor or the electron affinity of the n-type semiconductor layer and the work function of a metal layer which is brought into contact with the semiconductor, so as to reduce the contact resistance as compared to the case when Al or Ag is used as an electrode. The selected metal layer may be arranged between the electrode formed from Al or Ag and the semiconductor or may be substituted for the n- or p-type semiconductor.
    Type: Application
    Filed: March 2, 2009
    Publication date: January 6, 2011
    Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ohmi, Tetsuya Goto, Kouji Tanaka, Yuichi Sano
  • Publication number: 20100275981
    Abstract: An apparatus and method for manufacturing photoelectric conversion elements, and a photoelectric conversion element, the apparatus and method being capable of highly efficiently forming a film at a high speed with microwave plasma, preventing oxygen from mixing, and reducing the number of defects. The invention provides a photoelectric conversion element manufacturing apparatus 100 that forms a semiconductor stack film on a substrate by using microwave plasma CVD.
    Type: Application
    Filed: December 12, 2008
    Publication date: November 4, 2010
    Applicants: TOKYO ELECTRON LIMITED, TOHOKU UNIVERSITY
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Tetsuya Goto, Kouji Tanaka
  • Publication number: 20100236999
    Abstract: A spraying means is arranged on the scum-flowing wall surface side of wall surfaces forming a scum inlet of a scum discharging mechanism. The spraying means sprays pressured water upward along the wall surface on the scum-flowing side from when a part of the scum inlet is submerged in water until the scum begins to flow into the scum inlet. As a result, even large lumps of scum exceeding 10 cm in thickness (diameter) may be lead smoothly into a pipe by the pressured water, and the amount of discharged water accompanying scum discharge may be reduced to 1/20 to 1/30 than by a conventional scum removing apparatus.
    Type: Application
    Filed: October 12, 2007
    Publication date: September 23, 2010
    Inventors: Hideo Utsunomiya, Takao Abe, Kouji Tanaka
  • Publication number: 20100084717
    Abstract: Provided is a semiconductor device in which occurrence of humps can be suppressed and variations in characteristics of the semiconductor device can be suppressed. The semiconductor device includes: an element isolation film (200) formed in a semiconductor layer, the element isolation film (200) defining an element formation region; a gate electrode (130) formed above the element formation region, the gate electrode (130) having ends respectively extending above the element isolation film (200); and impurity regions (110) which are to be a source region and a drain region which are formed in the element formation region so as to sandwich therebetween a channel formation region immediately under the gate electrode (130), the gate electrode (130) including at each of the ends thereof a high work function region (124) in which work function is higher than work function in other regions over at least a part of an interface between the element formation region and the element isolation film (200).
    Type: Application
    Filed: September 15, 2009
    Publication date: April 8, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kouji Tanaka
  • Publication number: 20100032772
    Abstract: A semiconductor device includes an element isolation film formed on a semiconductor substrate surface of one conductivity type, a gate electrode having one pair of end portions located on a boundary between an element isolation film and an element forming region, a source region and a drain region of a reverse conductivity type arranged to sandwich a region immediately below a gate electrode, and an impurity diffusion region of the one conductivity type formed in the element forming region. The source region is separated from a region on a boundary side between the element isolation film and the element forming region in the region immediately below the gate electrode in the element forming region. In the impurity diffusion region, a portion adjacent to the region on the boundary side is arranged between the source region and the element isolation film, and is in contact with the source region and the region on the boundary side.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 11, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Kouji Tanaka
  • Publication number: 20090320756
    Abstract: A disclosed microwave plasma processing apparatus includes a process chamber whose inside may be maintained at a reduced pressure; a susceptor that is provided in the process chamber and holds a substrate; a gas supplying portion configured to supply a gas to the process chamber; a microwave generating portion that generates microwaves; a plasma introducing portion that is arranged to oppose the susceptor and introduces the microwaves generated by the microwave generating portion to the process chamber; and a mesh member arranged between the plasma introducing portion and the susceptor.
    Type: Application
    Filed: June 19, 2009
    Publication date: December 31, 2009
    Inventor: KOUJI TANAKA
  • Publication number: 20090263428
    Abstract: Provided is an artificial lymph node that is persistently effective in cancer treatment in vivo.
    Type: Application
    Filed: November 14, 2007
    Publication date: October 22, 2009
    Applicant: RIKEN
    Inventors: Takeshi WATANABE, Kouji TANAKA
  • Publication number: 20090243044
    Abstract: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern.
    Type: Application
    Filed: March 18, 2009
    Publication date: October 1, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Kouji Tanaka, Seiya Isozaki
  • Patent number: 7518849
    Abstract: A production method of a multilayer electronic device having an element body configured by alternately stacked dielectric layers formed by using dielectric paste and internal electrode layers formed by using conductive paste: wherein an adding quantity of a co-material included in conductive paste for forming internal electrode layers at the outermost positions in the stacking direction is larger than an adding quantity of a co-material included in conductive paste for forming internal electrode layers at the center position in the stacking direction when adding conductive particles and co-material particles to the conductive paste.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: April 14, 2009
    Assignee: TDK Corporation
    Inventors: Kazushige Ito, Kouji Tanaka, Makoto Takahashi, Akitoshi Yoshii, Masayuki Okabe
  • Publication number: 20090053900
    Abstract: A processing apparatus includes a process container having a placing table for placing a processing object, an exhaust system having vacuum pumps and a pressure control valve for exhausting atmosphere in the process container. A gas injection unit having a gas ejection hole is provided in the process container, as well as a gas supplying unit for supplying a process gas to the gas injection unit. The entire process apparatus is controlled by a controlling unit. The control unit controls the exhaust system and the gas supplying unit. When starting a predetermined process, the process gas at a flow rate greater than a prescribed flow rate is supplied for a short time while exhausting the atmosphere in the process container by the exhaust system, and then the process gas at a prescribed flow rate is supplied.
    Type: Application
    Filed: April 6, 2007
    Publication date: February 26, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Nozawa, Koji Kotani, Kouji Tanaka
  • Patent number: 7489005
    Abstract: An EEPROM having a nonvolatile memory cell is provided. The nonvolatile memory cell has a first MOS transistor and a second MOS transistor. The first MOS transistor and the second MOS transistor have a gate electrode in common, the gate electrode being a floating gate electrically isolated from a surrounding circuitry. The first MOS transistor and the second MOS transistor are of a same conductivity type.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: February 10, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kouji Tanaka
  • Patent number: 7489550
    Abstract: An EEPROM (Electrically Erasable and Programmable Read Only Memory) has a first MOS transistor and a second MOS transistor. The first MOS transistor and the second MOS transistor have a common gate electrode and constitute one memory cell. A program operation and an erase operation are carried out by using the first MOS transistor. A read operation is carried out by using the second MOS transistor.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: February 10, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kouji Tanaka
  • Patent number: 7435360
    Abstract: A manufacturing method of conductive paste comprising arranging process (S20 to S23) of ceramics particles, arranging process (S10 to S14) of wetted metal particles, forming process (S30) of slurry wherein metal particles and ceramics particles are mixed and dispersion treatment process (S32) by applying collision to the slurry. The arranging process of wetted metal particles comprises, a process (S12) of adding solvent, compatible with organic component in conductive paste and incompatible with water, to undried water washed metal particles, a process (S18) of adding surfactant, a process (S14) of separating water from the metal particles and a process (S15) of adding acetone or the other second solvent.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: October 14, 2008
    Assignee: TDK Corporation
    Inventors: Kazuhiko Oda, Tetsuji Maruno, Akira Sasaki, Kouji Tanaka
  • Patent number: 7413699
    Abstract: A ceramic electronic element having improved the continuity of inner electrode layers while suppressing the decrease in adhesion between its dielectric layers and inner electrode layers and the deterioration in functions of the inner electrode layers, and a method of making the same are provided. In the method of making a ceramic capacitor (10) in accordance with the present invention, an electrode paste (22) is applied to a surface (20a) of a green sheet (20) and fired, so as to form a dielectric layer (12) laminated with an electrode layer (14). Since the electrode paste (22) is doped with a BaTiO3 powder, the adhesion between the dielectric layer (22) and inner electrode layer (14) after firing is significantly restrained from lowering, and the sintering start temperature of the electrode paste (22) is close to that of the green sheet (20).
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: August 19, 2008
    Assignee: TDK Corporation
    Inventors: Shuichi Miura, Tetsuji Maruno, Kazuhiko Oda, Akira Sasaki, Kouji Tanaka
  • Patent number: 7402867
    Abstract: In a semiconductor device, a plurality of first diffusion regions of a first conductive type are formed on a diffusion layer well of the first conductive type. A plurality of second diffusion regions of a second conductive type are formed on the diffusion layer well of the first conductive type. An impurity concentration of each of the plurality of first and second diffusion regions is desirably higher than that of the diffusion layer well. The plurality of first diffusion regions are connected to a first common node as an anode and the plurality of second diffusion regions are connected to a second common node as a cathode.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: July 22, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Kouji Tanaka
  • Publication number: 20070236862
    Abstract: A production method of a multilayer electronic device having an element body configured by alternately stacked dielectric layers formed by using dielectric paste and internal electrode layers formed by using conductive paste: wherein an adding quantity of a co-material included in conductive paste for forming internal electrode layers at the outermost positions in the stacking direction is larger than an adding quantity of a co-material included in conductive paste for forming internal electrode layers at the center position in the stacking direction when adding conductive particles and co-material particles to the conductive paste.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 11, 2007
    Applicant: TDK CORPORATION
    Inventors: Kazushige Ito, Kouji Tanaka, Makoto Takahashi, Akitoshi Yoshii, Masayuki Okabe
  • Publication number: 20070223177
    Abstract: A production method of a multilayer electronic device having an element body configured by alternately stacked dielectric layers and internal electrode layers: wherein a particle diameter ? of conductive particles and a particle diameter ? of co-material particles satisfies a relationship of ?/?=0.8 to 8.0, and an adding quantity of the co-material particles to the conductive paste is larger than 30 wt % and smaller than 65 wt %.
    Type: Application
    Filed: March 20, 2007
    Publication date: September 27, 2007
    Applicant: TDK CORPORATION
    Inventors: Kazushige Ito, Kouji Tanaka, Makoto Takahashi, Akitoshi Yoshii, Masayuki Okabe