Patents by Inventor Kouji Yoshimaru

Kouji Yoshimaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7378332
    Abstract: Provided are a bonding substrate whose defective bonding portion in a peripheral region of an active layer has been removed by a polishing applied thereto after a surface grinding, a manufacturing method of the same substrate and wafer periphery pressing jigs. After the surface grinding, a periphery removing polishing is applied from an active layer wafer side of a bonding wafer so that a peripheral region of the active layer may be removed and a central region thereof may be left un-removed. Consequently, a periphery grinding and a periphery etching according to the prior art can be eliminated. Furthermore, an etch pit on a circumferential face of a wafer which could be caused by the periphery etching and a contamination or a scratching in an SOI layer which could be caused by a silicon oxide film left un-ground-off can be prevented, thereby achieving high yield and low cost.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: May 27, 2008
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Shinichi Tomita, Kouji Yoshimaru
  • Publication number: 20050014347
    Abstract: Provided are a bonding substrate whose defective bonding portion in a peripheral region of an active layer has been removed by a polishing applied thereto after a surface grinding, a manufacturing method of the same substrate and wafer periphery pressing jigs. After the surface grinding, a periphery removing polishing is applied from an active layer wafer side of a bonding wafer so that a peripheral region of the active layer may be removed and a central region thereof may be left un-removed. Consequently, a periphery grinding and a periphery etching according to the prior art can be eliminated. Furthermore, an etch pit on a circumferential face of a wafer which could be caused by the periphery etching and a contamination or a scratching in an SOI layer which could be caused by a silicon oxide film left un-ground-off can be prevented, thereby achieving high yield and low cost.
    Type: Application
    Filed: May 2, 2003
    Publication date: January 20, 2005
    Inventors: Shinichi Tomita, Kouji Yoshimaru