Abstract: In a wireless communication system, when data communication is performed between a relay device and a terminal (in a second path), the same amount of data is required to be transferred between a base station and the relay device (in a third path). An amount of wireless communication resources required is obtained by adding an amount inversely proportional to a capacity of each of the second and third wireless transmission-paths. Therefore, the amount inversely proportional to the capacity of the third path is consumed in excess. Based on a channel quality of a first wireless channel between the base station and the terminal, a channel quality of a second wireless channel between the terminal and the relay station, and a channel quality of a third wireless channel between the base station and the relay station, it is determined whether data communication between the base station and the terminal is relayed.

Abstract: In a wireless communication system, when data communication is performed between a relay device and a terminal (in a second path), the same amount of data is required to be transferred between a base station and the relay device (in a third path). An amount of wireless communication resources required is obtained by adding an amount inversely proportional to a capacity of each of the second and third wireless transmission-paths. Therefore, the amount inversely proportional to the capacity of the third path is consumed in excess. Based on a channel quality of a first wireless channel between the base station and the terminal, a channel quality of a second wireless channel between the terminal and the relay station, and a channel quality of a third wireless channel between the base station and the relay station, it is determined whether data communication between the base station and the terminal is relayed.

Abstract: A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.