Abstract: Structures for a cavity-mounted chip and methods of fabricating a structure for a cavity-mounted chip. The structure comprises a laser chip including a body attached to a substrate. The laser chip has an output, and the body of the laser chip has a bottom surface spaced from the substrate by a gap. The structure further comprises a first adhesive in the first gap and a second adhesive positioned in the first gap between the first adhesive and the output of the laser chip. The first adhesive has a first thermal conductivity, the second adhesive has a second thermal conductivity, and the first thermal conductivity of the first adhesive is greater than the second thermal conductivity of the second adhesive.

Abstract: Structures for a waveguide core and methods of fabricating such structures. The structure comprises a waveguide core including a section having a first trapezoidal portion and a second trapezoidal portion stacked with the first trapezoidal portion. The first trapezoidal portion has a first trapezoidal shape, and the second trapezoidal portion has a second trapezoidal shape different from the first trapezoidal shape.

Abstract: Structures for a cavity included in a photonics chip and methods of fabricating a structure for a cavity included in a photonics chip. The structure includes a substrate, a back-end-of-line stack having interlayer dielectric layers on the substrate, and a cavity penetrating through the back-end-of-line stack and into the substrate. The cavity includes first sidewalls and second sidewalls, and the second sidewalls have an alternating arrangement with the first sidewalls to define non-right-angle corners.

Abstract: A photonic integrated circuit (PIC) structure includes an active region in at least an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are over the active region, and an opening is defined through the plurality of dielectric interconnect layers. The opening extends to at least the active layer. A barrier is within the plurality of dielectric interconnect layers and surrounding the opening. An optical element is positioned in the opening. The barrier prevents stress damage, such as cracks and/or delaminations, from propagating from or to the opening, and maintains the hermetic seal of the PIC structure.

Abstract: Structures for a cavity included in a photonics chip and methods of fabricating a structure for a cavity included in a photonics chip. The structure includes a substrate, a back-end-of-line stack having interlayer dielectric layers on the substrate, and a cavity penetrating through the back-end-of-line stack and into the substrate. The cavity includes first sidewalls and second sidewalls, and the second sidewalls have an alternating arrangement with the first sidewalls to define non-right-angle corners.

Abstract: A photonic integrated circuit (PIC) structure includes an active region in at least an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are over the active region, and an opening is defined through the plurality of dielectric interconnect layers. The opening extends to at least the active layer. A barrier is within the plurality of dielectric interconnect layers and surrounding the opening. An optical element is positioned in the opening. The barrier prevents stress damage, such as cracks and/or delaminations, from propagating from or to the opening, and maintains the hermetic seal of the PIC structure.

Abstract: Disclosed are embodiments of a microelectronics package that includes: first and second substrates (each having first and second sides); a chip; and a multi-element antenna connected to the chip. The chip is mounted on the first side of the first substrate. A first antenna element of the antenna is on the second side of the first substrate and electrically connected to the chip. The first side of the second substrate is adhered to the second side of the first substrate (i.e., covering the first antenna element). A second antenna element of the antenna is on the second side of the second substrate overlaying the first antenna element and physically separated therefrom by at least one ultra-low-K dielectric region within the first side of the second substrate and/or the second side of the first substrate. Optionally, the package includes multiple chips and/or multiple antennas. Also disclosed are associated method embodiments.

Abstract: A semiconductor device is provided, which includes a multi-layered substrate having an interposed polymeric film and a device layer arranged over the multi-layered substrate.

Abstract: Disclosed are embodiments of a microelectronics package that includes: first and second substrates (each having first and second sides); a chip; and a multi-element antenna connected to the chip. The chip is mounted on the first side of the first substrate. A first antenna element of the antenna is on the second side of the first substrate and electrically connected to the chip. The first side of the second substrate is adhered to the second side of the first substrate (i.e., covering the first antenna element). A second antenna element of the antenna is on the second side of the second substrate overlaying the first antenna element and physically separated therefrom by at least one ultra-low-K dielectric region within the first side of the second substrate and/or the second side of the first substrate. Optionally, the package includes multiple chips and/or multiple antennas. Also disclosed are associated method embodiments.

Abstract: A semiconductor device is provided, which includes a multi-layered substrate having an interposed polymeric film and a device layer arranged over the multi-layered substrate.

Abstract: Disclosed are embodiments of a microelectronics package that includes: first and second substrates (each having first and second sides); a chip; and a multi-element antenna connected to the chip. The chip is mounted on the first side of the first substrate. A first antenna element of the antenna is on the second side of the first substrate and electrically connected to the chip. The first side of the second substrate is adhered to the second side of the first substrate (i.e., covering the first antenna element). A second antenna element of the antenna is on the second side of the second substrate overlaying the first antenna element and physically separated therefrom by at least one ultra-low-K dielectric region within the first side of the second substrate and/or the second side of the first substrate. Optionally, the package includes multiple chips and/or multiple antennas. Also disclosed are associated method embodiments.

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).

Abstract: A multi-chip semiconductor device with multi-level structure including a substrate with a top substrate surface, a cavity with a depth in the substrate, a first chip having a top first chip surface with a first chip height, optionally including a second chip having a top second chip surface with a second chip height, and a connecting passive chip bridging the first chip, the second chip and the substrate by solder bumps wherein the solder bumps enable the connecting passive chip to be level.

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).

Abstract: A photonic integrated circuit (PIC) package includes a PIC die including electro-optical circuitry having an optical waveguide system therein and a V-groove fiber optic receptacle on a first surface thereof. The V-groove fiber optic receptacle positions an optical element, e.g., optical fiber(s), for optical coupling with the optical waveguide system. An optical element is operatively coupled to the optical waveguide system and positioned in the V-groove fiber optic receptacle. A magnetic force inducer (MFI) is positioned to forcibly direct the optical element into position in the V-groove fiber optic receptacle in response to application of a magnetic field from a direction opposite the V-groove fiber optic receptacle in the first surface. During assembly, a magnetic field may be applied to the MFI to generate the magnetic force. After adhering the optical element, the magnetic field may remain to allow the PIC package to be moved with more security.

Abstract: Various embodiments include integrated circuit (IC) package structures. In some cases, an IC package includes: a carrier having a recess; a plurality of IC chips coupled with the carrier inside the recess, the plurality of IC chips each including a plurality of connectors; a thermally conductive material between the plurality of IC chips and the carrier within the recess, the thermally conductive material coupling the plurality of IC chips with the carrier; a dielectric layer contacting the plurality of IC chips and the carrier; a redistribution layer (RDL) contacting the dielectric layer and the plurality of connectors, the RDL including a plurality of fan-out vias extending from the plurality of connectors and at least one connector coupling adjacent IC chips in the plurality of IC chips; and a set of solder balls contacting the RDL and connected with the plurality of fan-out vias.