Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs respectively comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on their corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source, respectively. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are respectively comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Abstract: Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.

Abstract: A memory cell of a SRAM comprises two drive MISFET and two vertical MISFETs. The p channel vertical MISFET are formed above the n channel drive MISFET. The vertical MISFETs respectively mainly comprise a square pole laminate comprising a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film comprising silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: Disclosed herein is a semiconductor device wherein a thyristor protective element and a trigger element are provided in a semiconductor layer formed on a buried insulating layer, and a trigger electrode (gate) of the thyristor protective element and a back gate of the trigger element are provided in the same p well and electrically connected to each other to thereby drive the thyristor protective element based on a substrate current produced by the breakdown of the trigger element.

Abstract: An information retention capability based on a memory cell which includes pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (G03) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.

Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

Abstract: In order to eliminate the difference in ESD resistance caused by polarities of excessive voltages applied to an external terminal and enhance ESD resistance of a semiconductor integrated circuit device to both the positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.

Abstract: An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.

Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

Abstract: The write performance and erasion performance of a nonvolatile semiconductor memory having as its memory elements MOSFETs in each of which a floating gate electrode is formed on each of the two sidewalls of a control gate electrode are to be improved, and the read performance is also to be improved. Part of the control gate electrode is extended above the floating gate electrodes on its two sidewalls. A source region and a drain region are formed alongside the outer boundaries of the floating gate electrodes so,that electric charges can be separately injected into the two floating gate electrodes.

Abstract: In order to eliminate a difference in ESD resistance caused by the polarities of excessive voltages applied to an external terminal and enhance the ESD resistance of a semiconductor integrated circuit device to both positive and negative overvoltages, a protection element having a thyristor structure, for protecting an internal circuit from the positive overvoltage and a protection element made up of a diode D1 for protecting the internal circuit from the negative overvoltage are provided between the external terminal and a ground potential.

Abstract: An information retention capability based on a memory cell which comprises a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.

Abstract: Semiconductor regions for the suppression of short channel effects are not provided for a pMIS and an nMIS that constitute an inverter circuit of an input first stage of an I/O buffer circuit, whereas semiconductor regions for the suppression of short channel effects are provided for pMIS and nMIS of inverter circuits subsequent to the next stage of an I/O buffer circuit.

Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

Abstract: The write performance and erasion performance of a nonvolatile semiconductor memory having as its memory elements MOSFETs in each of which a floating gate electrode is formed on each of the two sidewalls of a control gate electrode are to be improved, and the read performance is also to be improved. Part of the control gate electrode is extended above the floating gate electrodes on its two sidewalls. A source region and a drain region are formed alongside the outer boundaries of the floating gate electrodes so that electric charges can be separately injected into the two floating gate electrodes.