Patents by Inventor Kousuke Sakoda

Kousuke Sakoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5485612
    Abstract: A computer system has a plurality of processors, each having a local memory. An expression is represented by operands and operations and is expressed in a form of a tree. The operands are assigned to leaf nodes of the tree and the operations are assigned to interior nodes. Processors which store an operand represented by a leaf node are assigned to the leaf node. The tree is traced in a bottom-up fashion to determine a set of candidate processors to be assigned to each of the interior nodes. The candidate processors are determined from processors which are assigned to children nodes of each interior node in accordance with a majority method. The majority method is based on a rule that a processor which is most frequently assigned to the children nodes of an interior node is determined as a candidate processor. A root processor is assigned to a root node of the interior nodes from the candidate processors.
    Type: Grant
    Filed: February 4, 1992
    Date of Patent: January 16, 1996
    Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd., Hitachi Nuclear Engineering Co., Ltd.
    Inventors: Hiroshi Ota, Kousuke Sakoda, Tetsuo Saito, Eiichiro Maeda, Toshiyuki Yamamoto
  • Patent number: 5293594
    Abstract: In order to divide a memory addressed unidimensionally into a plurality of memory areas and to manage efficiently these memory areas, the address to be accessed inside the memory is determined on a software basis by a computer instruction by use of the value of a first pointer designating each memory area and the value of a second pointer designating the relative address in the designated memory area.
    Type: Grant
    Filed: April 3, 1990
    Date of Patent: March 8, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Tohru Nojiri, Shunpei Kawasaki, Tan Watanabe, Kousuke Sakoda
  • Patent number: 5043873
    Abstract: A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data.
    Type: Grant
    Filed: August 17, 1989
    Date of Patent: August 27, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Akira Muramatsu, Kousuke Sakoda, Ikuo Yoshihara, Kazuo Nakao, Makoto Nohmi, Naoki Hamanaka, Shigeo Nagashima, Teruo Tanaka
  • Patent number: 4951193
    Abstract: In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.
    Type: Grant
    Filed: August 14, 1987
    Date of Patent: August 21, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Akira Muramatsu, Kousuke Sakoda, Ikuo Yoshihara, Kazuo Nakao, Makoto Nohmi, Naoki Hamanaka, Shigeo Nagashima, Teruo Tanaka
  • Patent number: 4794528
    Abstract: In order to highly speed up the pattern matching of tree structured data in a logic programming language, the priority order is set when the data owned by the individual nodes of a tree structure are to be transversely sought, and the tree structured data are expressed in a vector type, in which they are arranged in that priority order, so that they are compared consecutively from the head for each element of the vector.
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: December 27, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Hirose, Kazuo Nakao, Kousuke Sakoda, Youichi Takeuchi
  • Patent number: 4692896
    Abstract: A method of processing a plurality of different code systems for an information processing apparatus including an operating system, comprises a step of inputting a source program, and a compiling step of analyzing meaning of the source program to thereby create a series of instructions and data required for executing a processing equivalent to the meaning of the source program.
    Type: Grant
    Filed: July 8, 1985
    Date of Patent: September 8, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Kousuke Sakoda, Masahiro Kainaga, Hidehiko Akita, Fumiya Murata, Yoshitake Nakaosa
  • Patent number: 4665478
    Abstract: A computer system comprises a memory for storing communication history information between a terminal and an execution program, and an output message file for storing sets of communication history conditions and output messages corresponding to those conditions. When the terminal issues a message output request, only the output message that meets the communication history condition is selected from the output message file and outputted to the terminal.
    Type: Grant
    Filed: August 14, 1984
    Date of Patent: May 12, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Hirose, Kousuke Sakoda, Tomihiko Kojima, Hidehiko Akita, Tsutomu Miyairi
  • Patent number: 4491912
    Abstract: A data processing system having a first storage for storing therein microprograms; an address register for supplying an instruction address of a microprogram to be executed into said first storage; a stack unit having a stack area for storing therein a return address of the microprogram; a first control unit responsive to a microinstruction for instructing a microsubroutine call to store the return address of the microinstruction in the stack unit, and responsive to a microinstruction for instructing return from the microsubroutine to restore the return address of the microinstruction from said stack unit; a second control unit for monitoring an interrupt request; a second storage for saving therein the content of said stack unit; a status register having a field for indicating the acceptance of the interrupt request in the course of the execution of the microprogram, and a third control unit responsive to the detection of the interrupt request by the second control unit in the course of the execution of the
    Type: Grant
    Filed: March 16, 1982
    Date of Patent: January 1, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Kainaga, Kousuke Sakoda, Hiroaki Nakanishi