Abstract: The objective of the present invention is to present a buffer circuit by which a load can be driven at a high speed while restraining an increase in power consumption. A current input to npn transistor Q1 via node N1 is detected by current detection circuit 1. At bias control circuit 2, base voltage of npn transistor Q2 is regulated in such a manner that the current of npn transistor Q2 decreases in accordance with an increase in said detected current, and the current of npn transistor Q2 increases in accordance with a decrease in the detected current. As a result, because transient current which can flow to the load can be increased, even when load capacitor CL has a large capacitance or when the frequency is high, the output voltage can quickly follow a change in the input voltage, so that distortion of the output voltage waveform can be restrained.

Abstract: The objective of the present invention is to present a buffer circuit by which a load can be driven at a high speed while restraining an increase in power consumption. A current input to npn transistor Q1 via node N1 is detected by current detection circuit 1. At bias control circuit 2, base voltage of npn transistor Q2 is regulated in such a manner that the current of npn transistor Q2 decreases in accordance with an increase in said detected current, and the current of npn transistor Q2 increases in accordance with a decrease in the detected current. As a result, because transient current which can flow to the load can be increased, even when load capacitor CL has a large capacitance or when the frequency is high, the output voltage can quickly follow a change in the input voltage, so that distortion of the output voltage waveform can be restrained.

Abstract: A timer circuit having an oscillator circuit that has low power consumption and a stable frequency of the output signal. Timer circuit 10 has highly stable oscillator 21, counter 22 and frequency dividing value controller 24. Highly stable oscillator 21 generates a standard signal at a prescribed frequency. Counter 22 determines the frequency ratio of the frequency of the internal signal to the frequency of the standard signal, and, corresponding to the frequency ratio, frequency dividing value controller 24 changes the frequency dividing value of frequency divider 12. Because the difference between the frequency of the internal signal and the frequency of the standard signal can be known from the frequency ratio, it is possible to perform control such that the frequency of the output signal is kept stable at a prescribed frequency.

Abstract: An oscillation circuit uses a SAW oscillator and is able to control the oscillation frequency easily and correct the temperature characteristic of the oscillator so that an oscillation signal with high temperature stability can be generated. A clock signal CLK having a prescribed frequency difference from the ideal oscillation frequency is generated by the SAW oscillator 10. Register 30 is driven by a frequency-divided clock signal obtained by dividing the frequency of the clock signal at a predetermined frequency division rate. In-phase signal SI and quadrature signal SQ generated corresponding to the data Da that is incremented by a prescribed addition value F every period of the frequency-divided clock signal are output, and the clock signal is IQ-modulated on the basis of these signals. The frequency error of clock signal CLK can be corrected, and an output signal Sout having near ideal oscillation frequency can be obtained.

Abstract: A circuit for removing a spurious component contained in the output signal in the locked state of a PLL circuit in a fractional frequency division system. For frequency synthesizer 1 in this invention, there is a period in which the current sunk by charge pump circuit 35 and the current output from it are different from each other, and the ON start time of the upper operation transistor on the source side is different from that of the lower operation transistor on the sink side. Consequently, the output signal of charge pump circuit 35 is free of the error component generated in the prior art due to that fact that the ON start times of the upper operation transistor and lower operation transistor are close to each other and the operation transistor that turns ON earlier affects the other operation transistor. Consequently, when a compensating current from compensating circuit 37 is superimposed on the output signal, it is possible to eliminate the ripple current completely.

Abstract: The present invention pertains to a type of frequency synthesizer which can correctly compensate for the ripple current. Frequency synthesizer 1 has PLL loop containing oscillator 31 and charge pump circuit 35. Also, the frequency synthesizer has compensating circuit 41 and correcting circuit 43. Said correcting circuit 43 has sense amplifier 44, up/down counter 45, and DA converter 40. The compensating circuit superimposes a compensating current onto the output current of charge pump circuit 35 which generates the control signal of oscillator 31, and it compensates for the ripple current contained in the output current. After the PLL loop is locked, sense amplifier 44 detects the ripple current with the superimposed compensating current, and based on the detection result, up/down counter 45 and DA converter 40 control compensating circuit 43, and the difference between the ripple current and the compensating current is reduced.

Abstract: Frequency synthesizer (1) has compensation circuit (45) and correction circuit (10). Compensation circuit (45) has compensation capacitor (46), while correction circuit (10) has detection capacitor (23). Correction circuit (10) charges/discharges detection capacitor (23) corresponding to the control signal of the PLL loop to generate a reference voltage. Compensation circuit (45) applies a voltage to compensation capacitor (46) on the basis of the reference voltage to cancel the ripple current included in the control signal. By making the time for charging/discharging detection capacitor (23) equal to one period of a comparison signal obtained by dividing the frequency of the external output signal of the PLL loop, it is possible to generate a reference voltage which can follow changes in the external output signal. Consequently, the ripple current can be correctly cancelled out by following the changes in the external output signal.

Abstract: In a frequency synthesizer 1 that has a high spurious component elimination ratio, if the integer frequency division value is changed and a fractional frequency division value is to be generated, rounding circuit 6 rounds the random number generated by random number generation circuit 7. Based on the integer value that is thereby generated, frequency division value control circuit 5 generates an integer frequency division value. Because the integer frequency division value changes based on a random number, there is no regularity, and spurious components are never generated in output signal OUT. Even if compensation circuit 37 generates a compensation current and superimposes it on the output of charge pump circuit 35, the influence of the ripple current output from charge pump circuit 35 cannot be completely eliminated.

Abstract: An oscillation circuit uses a SAW oscillator and is able to control the oscillation frequency easily and correct the temperature characteristic of the oscillator so that an oscillation signal with high temperature stability can be generated. A clock signal CLK having a prescribed frequency difference from the ideal oscillation frequency is generated by the SAW oscillator 10. Register 30 is driven by a frequency-divided clock signal obtained by dividing the frequency of the clock signal at a predetermined frequency division rate. In-phase signal SI and quadrature signal SQ generated corresponding to the data Da that is incremented by a prescribed addition value F every period of the frequency-divided clock signal are output, and the clock signal is IQ-modulated on the basis of these signals. The frequency error of clock signal CLK can be corrected, and an output signal Sout having near ideal oscillation frequency can be obtained.

Abstract: Objective

Abstract: A timer circuit that has low power consumption and a stable frequency of the output signal. Timer circuit 10 of this invention has highly stable oscillator 21, counter 22 and frequency dividing value controller 24. Highly stable oscillator 21 generates a standard signal at a prescribed frequency. Counter 22 determines the frequency ratio of the frequency of the internal signal to the frequency of the standard signal, and, corresponding to said frequency ratio, frequency dividing value controller 24 changes the frequency dividing value of frequency divider 12. Because the difference between the frequency of the internal signal and the frequency of the standard signal can be known from the frequency ratio, it is possible to perform control such that the frequency of the output signal is kept stable at a prescribed frequency.

Abstract: A circuit for removing a spurious component contained in the output signal in the locked state of a PLL circuit in a fractional frequency division system. For frequency synthesizer 1 in this invention, there is a period in which the current sunk by charge pump circuit 35 and the current output from it are different from each other, and the ON start time of the upper operation transistor on the source side is different from that of the lower operation transistor on the sink side. Consequently, the output signal of charge pump circuit 35 is free of the error component generated in the prior art due to that fact that the ON start times of the upper operation transistor and lower operation transistor are close to each other and the operation transistor that turns ON earlier affects the other operation transistor. Consequently, when a compensating current from compensating circuit 37 is superimposed on the output signal, it is possible to eliminate the ripple current completely.

Abstract: An R-2R type DA converter where the resistance value of the weighting resistors is set to a value calculated by adding the resistance value error to twice the standard resistance value. The resistance value of the terminating resistor (third-value resistor) is set to a value wherein the resistance value error is subtracted from twice the standard resistance value. With these resistance values, when a digital data signal is incremented even if the output voltage immediately before the digital signal is incremented is larger than the output voltage immediately after the digital signal is incremented, the output voltage immediately after the digital signal is incremented will not be excessively large compared to the output voltage immediately after the digital signal is incremented.

Abstract: A frequency synthesizer that can accurately compensate for ripple current. The frequency synthesizer 1 having a PLL loop containing an oscillator 31 and a charge pump circuit 35 has a detector circuit 40 and a delay circuit 39. The detector circuit 40, by detecting a ripple current with a superimposed compensating current, detects the time difference between the output time of the compensating current and the output time of the ripple current, and since the delay circuit 39 delays one or both of the output time of the compensating current and the output time of the ripple current based on that detection result, the time difference for the output times can be made small, and if a compensating current is supplied that is equal to the ripple current, it becomes possible to accurately remove the ripple current.

Abstract: In a frequency synthesizer 1 that has a high spurious component elimination ratio, if the integer frequency division value is changed and a fractional frequency division value is to be generated, rounding circuit 6 rounds the random number generated by random number generation circuit 7. Based on the integer value that is thereby generated, frequency division value control circuit 5 generates an integer frequency division value. Because the integer frequency division value changes based on a random number, there is no regularity, and spurious components are never generated in output signal OUT. Even if compensation circuit 37 generates a compensation current and superimposes it on the output of charge pump circuit 35, the influence of the ripple current output from charge pump circuit 35 cannot be completely eliminated.

Abstract: To provide a type of frequency synthesizer having excellent characteristics and free of spurious component in the output signal. In frequency synthesizer (2), frequency divider (32) makes the frequency division value change periodically; external output signal OUT output from oscillator (31) is divided by the average frequency division value to generate a comparative signal; phase comparator (34) compares the phase of the comparative signal with the phase of the reference clock signal; oscillator (31) is controlled such that the frequency of external output signal OUT becomes a value equal to the frequency of the reference clock signal times the average frequency division value; the voltage applied to compensation circuit (10) is changed abruptly, and a compensating current is generated, and the ripple current generated is cancelled in synchronization to the reference clock signal.

Abstract: The purpose of the present invention is to provide a frequency synthesizer which does not have spurious components. Automatic reference correcting circuit 4 is provided to frequency synthesizer 1 which changes the frequency division value of the divider and makes the frequency of external output signal (OUT) into a value equal to the frequency of the reference clock signal multiplied by the average frequency division value, charge pump circuit 35 measures the ripple component contained in the output control signal, and ripple correcting circuit 39 forms compensation current, which is superimposed on the control signal in order to minimize the ripple component. If composed for control circuit 55 to obtain the optimum compensation current and output to ripple correcting circuit 39 while negative feedback which minimizes the ripple component is being formed, output signal (OUT) which does not have spurious components can be obtained.

Abstract: A logic circuit contains a first transistor with a logic signal supplied to the base and having its collector connected to an output node. A second transistor has a collector connected to the emitter of the first transistor and an emitter connected to a reference potential, in which the collector current supplied to the first transistor corresponds to the level of the control signal supplied to the base. A p-channel insulated gate field-effect transistor is connected between the power supply and the output node, and a first bias circuit supplies a bias voltage to the gate of the p-channel insulated gate field-effect transistor as the load. An n-channel insulated gate field-effect transistor is connected between the power supply and the output node and parallel to the p-channel insulated gate field-effect transistor as the load, and a second bias circuit supplies a bias voltage to the gate of the n-channel insulated gate field-effect transistor.

Abstract: A logic circuit for implementing a flip-flop circuit that operates stably and at high speed at a low supply voltage of about 1 V. The logic circuit includes transistors 25,26,31 for forming a first current mirror circuit 2; transistors 27,28 for converting clock signals to current signals; transistors 19,22,23 for forming a second current mirror circuit 3; and transistors 20,21,24 forming a third current mirror circuit 4. These current mirror circuits supply a current nearly equal to the current from transistors 27,28 to the circuits connected respectively to those current mirror circuits. Transistors 29,30, current source 47, voltage source 50 and voltage comparison circuit 51 form a voltage maintenance circuit. Transistors 11,12 and resistors 41,42 form an input stage of a master D flip-flop D-FF, and transistors 13,14 form the signal-holding row of the master D flip-flop D-FF.

Abstract: A semiconductor integrated circuit for performing a current mirror function and capable of operating stably at a low supply voltage to yield an output current nearly equal to the reference current. The current mirror circuit includes a pair of horizontal type pnp transistors and a vertical type npn transistor having an area almost equal to that of either of the pair of horizontal transistors, the vertical type npn transistor being used as a reverse transistor. A current source supplies the base current of the horizontal transistors as well as the collector current of the vertical transistor. Because of its structure, it is possible for the vertical transistor to have a base area and static forward current transfer ratio greater than those of the horizontal transistors. Since the emitter area of the vertical transistor is large, even when it is used to function as a reverse transistor, its static forward current transfer ratio is high.