Abstract: In a pipeline computer, a store sub-instruction address is stored into a most recent address register as well as into an address buffer in response to a store request and a load sub-instruction address is supplied to a main memory in response to a load sub-instruction. When a store sub-instruction data is stored into a buffer following the storage of the store sub-instruction address into the most recent address register, the contents of the address buffer and the data buffer are transferred to a location of the main memory specified by the sub-instruction address. Main memory data is retrieved from a location specified by an associated load sub-instruction address. A match or a mismatch is detected between the address in the most recent address register and an address generated in response to a subsequent load sub-instruction.

Abstract: An address translation buffer control system includes multiple prioritized address translation buffers and circuitry for changing the contents of the buffers. When a desired address translation pair is not present in the buffer having the highest priority, the contents of the highest priority buffer are replaced with contents from a lower priority buffer. If a desired address translation pair is not present in any buffer, the contents of the lowest priority buffer are replaced.

Abstract: In an information processing apparatus of the type comprising a CPU, a memory device and input and output device, where a portion of the memory region storing a plurality of bytes as a unit of data to be stored overlaps a portion of the memory region to which the data are transferred, there are provided an address difference calculating circuit for calculating the difference of the addresses at the data transfer and data receiving sides, a comparator for comparing respective addresses, and a recurrent data pattern forming circuit for exchanging data between the memory region for storing the data and the memory region for receiving the data by a number corresponding to the difference of the addresses.