Abstract: A memory device includes memory cells, bit lines, active areas, and transistors formed in each active area and electrically coupling memory cells to corresponding bit lines. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line may include a first level portion and a second level portion.

Abstract: A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Abstract: A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: A rearview mirror tilt actuator comprises a clutch assembly that selectively transfers torque from an actuator motor to one of at least two output shafts based upon the speed of the motor. One output shaft can pivot the mirror about a first axis of rotation; another output shaft can pivot the mirror about a second axis of rotation. One output shaft can pivot the mirror housing; the other output shaft can extend and retract the mirror housing. At a low speed, the clutch assembly is disengaged, thus only the first output shaft is activated. At a high speed, the clutch assembly is engaged, thus both output shafts are activated The mirror assembly described herein also has an improved mass configuration which allows for lower moments of inertia in the direction of mirror travel.

Abstract: A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.

Abstract: A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.

Abstract: A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.