Abstract: A controller for interfacing a central processor unit (CPU) to a peripheral storage device which can be tested for proper operation independent of the peripheral storage device includes a sequencer, a buffer, a microprocessor and various error detection logic. A gate is coupled between the sequencer and the input of the peripheral storage device for enabling or disabling the transfer of data from the sequencer to the peripheral storage device and a multiplexer is coupled between the microprocessor, the output of the peripheral storage device and the sequencer for selecting inputs to the sequencer from either the microprocessor or the peripheral storage device. During a normal write operation, write signals are sent from the CPU to the sequencer through the buffer and then from the sequencer to the peripheral storage device through the gate.