Patents by Inventor Krishna Kumar Bhuwalka
Krishna Kumar Bhuwalka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128268Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: ApplicationFiled: December 11, 2023Publication date: April 18, 2024Inventors: Krishna Kumar BHUWALKA, Kyoung Min CHOI, Takeshi OKAGAKI, Dong Won KIM, Jong Chol KIM
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Patent number: 11876097Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: GrantFiled: August 6, 2021Date of Patent: January 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Krishna Kumar Bhuwalka, Kyoung Min Choi, Takeshi Okagaki, Dong Won Kim, Jong Chol Kim
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Patent number: 11515391Abstract: A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.Type: GrantFiled: October 14, 2020Date of Patent: November 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Krishna Kumar Bhuwalka, Seong-Je Kim, Jong-Chol Kim, Hyun-Woo Kim
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Publication number: 20210366910Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: ApplicationFiled: August 6, 2021Publication date: November 25, 2021Inventors: Krishna Kumar BHUWALKA, Kyoung Min CHOI, Takeshi OKAGAKI, Dong Won KIM, Jong Chol KIM
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Patent number: 11133311Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: GrantFiled: March 20, 2019Date of Patent: September 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Krishna Kumar Bhuwalka, Kyoung Min Choi, Takeshi Okagaki, Dong Won Kim, Jong Chol Kim
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Publication number: 20210050415Abstract: A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.Type: ApplicationFiled: October 14, 2020Publication date: February 18, 2021Inventors: Krishna Kumar BHUWALKA, Seong-Je KIM, Jong-Chol KIM, Hyun-Woo KIM
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Patent number: 10872972Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.Type: GrantFiled: October 7, 2019Date of Patent: December 22, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
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Patent number: 10840332Abstract: A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.Type: GrantFiled: January 16, 2019Date of Patent: November 17, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Krishna Kumar Bhuwalka, Seong-Je Kim, Jong-Chol Kim, Hyun-Woo Kim
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Publication number: 20200066725Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: ApplicationFiled: March 20, 2019Publication date: February 27, 2020Inventors: Krishna Kumar BHUWALKA, Kyoung Min CHOI, Takeshi OKAGAKI, Dong Won KIM, Jong Chol KIM
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Publication number: 20200044063Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.Type: ApplicationFiled: October 7, 2019Publication date: February 6, 2020Inventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
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Patent number: 10475907Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.Type: GrantFiled: May 8, 2017Date of Patent: November 12, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Krishna Kumar Bhuwalka, Gerben Doornbos, Matthias Passlack
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Publication number: 20190148489Abstract: A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.Type: ApplicationFiled: January 16, 2019Publication date: May 16, 2019Inventors: Krishna Kumar BHUWALKA, Seong-Je KIM, Jong-Chol KIM, Hyun-Woo KIM
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Patent number: 10217816Abstract: A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.Type: GrantFiled: October 18, 2016Date of Patent: February 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Krishna Kumar Bhuwalka, Seong-Je Kim, Jong-Chol Kim, Hyun-Woo Kim
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Patent number: 10164024Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.Type: GrantFiled: June 22, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Martin Christopher Holland, Georgios Vellianitis, Richard Kenneth Oxland, Krishna Kumar Bhuwalka, Gerben Doornbos
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Patent number: 10050111Abstract: A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.Type: GrantFiled: August 14, 2017Date of Patent: August 14, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka, Matthias Passlack
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Patent number: 9887272Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.Type: GrantFiled: December 30, 2015Date of Patent: February 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Richard Kenneth Oxland, Martin Christopher Holland, Krishna Kumar Bhuwalka
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Publication number: 20170365668Abstract: A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.Type: ApplicationFiled: August 14, 2017Publication date: December 21, 2017Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka, Matthias Passlack
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Publication number: 20170256609Abstract: A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.Type: ApplicationFiled: October 18, 2016Publication date: September 7, 2017Inventors: Krishna Kumar BHUWALKA, Seong-Je KIM, Jong-Chol KIM, Hyun-Woo KIM
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Publication number: 20170243961Abstract: Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.Type: ApplicationFiled: May 8, 2017Publication date: August 24, 2017Inventors: Krishna Kumar BHUWALKA, Gerben DOORNBOS, Matthias PASSLACK
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Patent number: 9735239Abstract: A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.Type: GrantFiled: April 11, 2012Date of Patent: August 15, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka, Matthias Passlack