Patents by Inventor Krishnakumar Rao Surugucchi
Krishnakumar Rao Surugucchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9880913Abstract: An apparatus comprises a storage controller coupled to at least one multi-region storage device. The at least one multi-region storage device comprises two or more storage regions, the two or more storage regions comprising a first storage region associated with a first set of failure characteristics and at least a second storage region associated with a second set of failure characteristics different than the first set of failure characteristics. The storage controller is configured to replicate in the second storage region at least a portion of data that is stored in the first storage region.Type: GrantFiled: December 14, 2015Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Bulent Abali, Mohammad Banikazemi, Timothy J. Chainer, James L. Hafner, Dan E. Poff, Krishnakumar Rao Surugucchi
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Publication number: 20170168908Abstract: An apparatus comprises a storage controller coupled to at least one multi-region storage device. The at least one multi-region storage device comprises two or more storage regions, the two or more storage regions comprising a first storage region associated with a first set of failure characteristics and at least a second storage region associated with a second set of failure characteristics different than the first set of failure characteristics. The storage controller is configured to replicate in the second storage region at least a portion of data that is stored in the first storage region.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Bulent Abali, Mohammad Banikazemi, Timothy J. Chainer, James L. Hafner, Dan E. Poff, Krishnakumar Rao Surugucchi
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Patent number: 8583868Abstract: Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller.Type: GrantFiled: August 29, 2011Date of Patent: November 12, 2013Assignee: International Business MachinesInventors: Wendy A. Belluomini, Binny S. Gill, James L. Hafner, Steven R. Hetzler, Venu G. Nayar, Daniel F. Smith, Krishnakumar Rao Surugucchi
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Publication number: 20130054873Abstract: Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller.Type: ApplicationFiled: August 29, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wendy A. Belluomini, Binny S. Gill, James L. Hafner, Steven R. Hetzler, Venu G. Nayar, Daniel F. Smith, Krishnakumar Rao Surugucchi
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Patent number: 8370715Abstract: Provided are a method, system, and article of manufacture for error checking addressable blocks in storage. Addressable blocks of data are stored in a storage in stripes, wherein each stripe includes a plurality of data blocks for one of the addressable blocks and at least one checksum block including checksum data derived from the data blocks for the addressable block. A write request is received to modify data in one of the addressable blocks. The write and updating the checksum are performed in the stripe having the modified addressable block. An indication is made to perform an error checking operation on the stripe for the modified addressable block in response to the write request, wherein the error checking operation reads the data blocks and the checksum in the stripe to determine if the checksum data is accurate. An error handling operation is initiated in response to determining that the checksum data is not accurate.Type: GrantFiled: April 12, 2007Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: James Lee Hafner, David Ray Kahler, Robert Akira Kubo, David Frank Mannenbach, Karl Allen Nielsen, James A. O'Connor, Krishnakumar Rao Surugucchi, Richard B. Stelmach
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Patent number: 8020032Abstract: A set of disks in a plurality of disk arrays are configured to have one or more spare partitions. Upon detecting a faulty disk in a faulty array, the method involves the steps of: (a) migrating data in the faulty array containing the faulty disk to one or more spare partitions; (b) reconfiguring the faulty array to form a new array without the faulty disk; (c) migrating data from one or more spare partitions in the set of disks to the reconfigured new array; (d) monitoring to identify when overall spare capacity falls below a predetermined threshold; and when the predetermined threshold is exceeded, scheduling a service visit for replacement of the failed disks.Type: GrantFiled: December 27, 2007Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Bulent Abali, Mohammad Banikazemi, James Lee Hafner, Daniel Edward Poff, Krishnakumar Rao Surugucchi
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Patent number: 7853823Abstract: A system (and method) for determining reconstruction formulas for partial strip reconstruction in a storage system in which a plurality of lost strips have been detected, includes using a combination of a direct reconstruction method and a sequential reconstruction method.Type: GrantFiled: August 6, 2009Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Veera W. Deenadhayalan, James Lee Hafner, Krishnakumar Rao Surugucchi
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Publication number: 20090313499Abstract: A system (and method) for determining reconstruction formulas for partial strip reconstruction in a storage system in which a plurality of lost strips have been detected, includes using a combination of a direct reconstruction method and a sequential reconstruction method.Type: ApplicationFiled: August 6, 2009Publication date: December 17, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veera W. Deenadhayalan, James Lee Hafner, Krishnakumar Rao Surugucchi
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Publication number: 20090172468Abstract: A set of disks in a plurality of disk arrays are configured to have one or more spare partitions. Upon detecting a faulty disk in a faulty array, the method involves the steps of: (a) migrating data in the faulty array containing the faulty disk to one or more spare partitions; (b) reconfiguring the faulty array to form a new array without the faulty disk; (c) migrating data from one or more spare partitions in the set of disks to the reconfigured new array; (d) monitoring to identify when overall spare capacity falls below a predetermined threshold; and when the predetermined threshold is exceeded, scheduling a service visit for replacement of the failed disks.Type: ApplicationFiled: December 27, 2007Publication date: July 2, 2009Applicant: International Business Machines CorporationInventors: Bulent Abali, Mohammad Banikazemi, James Lee Hafner, Daniel Edward Poff, Krishnakumar Rao Surugucchi
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Publication number: 20080256420Abstract: Provided are a method, system, and article of manufacture for error checking addressable blocks in storage. Addressable blocks of data are stored in a storage in stripes, wherein each stripe includes a plurality of data blocks for one of the addressable blocks and at least one checksum block including checksum data derived from the data blocks for the addressable block. A write request is received to modify data in one of the addressable blocks. The write and updating the checksum are performed in the stripe having the modified addressable block. An indication is made to perform an error checking operation on the stripe for the modified addressable block in response to the write request, wherein the error checking operation reads the data blocks and the checksum in the stripe to determine if the checksum data is accurate. An error handling operation is initiated in response to determining that the checksum data is not accurate.Type: ApplicationFiled: April 12, 2007Publication date: October 16, 2008Applicant: International Business Machines CorporationInventors: James Lee Hafner, David Ray Kahler, Robert Akira Kubo, David Frank Mannenbach, Karl Allen Nielsen, James A. O'Connor, Krishnakumar Rao Surugucchi, Richard B. Stelmach
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Patent number: 7073022Abstract: The present invention describes a method and system for interfacing a plurality of device controllers to an array of data storage devices by serial connection. The device controllers are coupled to a serial interface by a bus and the devices of the storage array are coupled to the serial interface by a serial connection. The serial interface receives controller signals through the bus and multiplexes the signals onto the serial connections of the storage array. Arbitration between the various device controllers seeking access to the storage array is resolved through bus protocol and through drive based reserve/release registers in the serial interface processor.Type: GrantFiled: May 23, 2002Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Mohamad H. El-Batal, Yoshihiro Fujie, Thomas Sing-Klat Liong, Krishnakumar Rao Surugucchi
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Patent number: 6928509Abstract: A method, system and apparatus for providing inter-connective access of a plurality of controllers to a plurality of serial storage devices are provided. Serial storage devices are provided with a serial operative connection to a data communication bridge. The bridge is operatively coupled to a plurality of controllers. The plurality of controllers is provided concurrent targeted connections to the set of serial storage devices. In one embodiment, InfiniBand® technology further increases the scalability and enhances the reliability of a data communication system provided with a plurality of (S-ATA) storage devices. The reliability of the data communication system is enhanced because if one controller should fail, another controller may still achieve and maintain access to the plurality of serial storage devices.Type: GrantFiled: August 1, 2002Date of Patent: August 9, 2005Assignee: International Business Machines CorporationInventor: Krishnakumar Rao Surugucchi
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Patent number: 6851005Abstract: Apparatus and methods are provided for efficiently implementing logical-device reservations in a cluster computer system. The apparatus includes cooperating controllers programmed in firmware around a distributed reservation table. The apparatus manages access to a logical device, with first and second nodes with respective bus controllers communicatively coupled to each other and to a logical device by means of a bus. The first controller receives a request to reserve the logical device and, in response, communicates a reservation request for the logical device over the bus to the second controller for execution by the second controller. In response to the communicated reservation request, the second controller reserves the logical device for the first node.Type: GrantFiled: March 3, 2000Date of Patent: February 1, 2005Assignee: International Business Machines CorporationInventors: Govindaraju Gnanasivam, Krishnakumar Rao Surugucchi
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Publication number: 20040024950Abstract: A method, system and apparatus for providing inter-connective access of a plurality of controllers to a plurality of serial storage devices are provided. Serial storage devices are provided with a serial operative connection to a data communication bridge. The bridge is operatively coupled to a plurality of controllers. The plurality of controllers is provided concurrent targeted connections to the set of serial storage devices. In one embodiment, InfiniBand® technology further increases the scalability and enhances the reliability of a data communication system provided with a plurality of (S-ATA) storage devices. The reliability of the data communication system is enhanced because if one controller should fail, another controller may still achieve and maintain access to the plurality of serial storage devices.Type: ApplicationFiled: August 1, 2002Publication date: February 5, 2004Applicant: International Business Machines CorporationInventor: Krishnakumar Rao Surugucchi
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Patent number: 6687765Abstract: Structure, method, and computer program for an explicitly tunable device controller. Method supports high-performance I/O without imposing additional overhead during normal input/output operations. Tuning is performed during explicit pre-I/O operation phase. In one embodiment, invention provides a method for tuning device controller operating characteristics to suit attributes of a data stream in which the method comprises: monitoring a data stream and collecting attributes of the monitored data stream; generating performance metrics of the data stream based on the collected attributes and a plurality of different assumed device controller configurations; comparing expected performance of the plurality of different device controller configurations for effectiveness with a future data stream having similar data stream type attributes to the monitored data stream; and selecting device controller characteristics to provide an effective match between the data stream type and the device controller configuration.Type: GrantFiled: January 16, 2001Date of Patent: February 3, 2004Assignee: International Business Machines CorporationInventors: Krishnakumar Rao Surugucchi, Bruce M. Cassidy
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Publication number: 20030221061Abstract: The present invention describes a method and system for interfacing a plurality of device controllers to an array of data storage devices by serial connection. The device controllers are coupled to a serial interface by a bus and the devices of the storage array are coupled to the serial interface by a serial connection. The serial interface receives controller signals through the bus and multiplexes the signals onto the serial connections of the storage array. Arbitration between the various device controllers seeking access to the storage array is resolved through bus protocol and through drive based reserve/release registers in the serial interface processor.Type: ApplicationFiled: May 23, 2002Publication date: November 27, 2003Applicant: International Business Machines CorporationInventors: Mohamad H. El-Batal, Yoshihiro Fujie, Thomas Sing-Klat Liong, Krishnakumar Rao Surugucchi
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Publication number: 20020095532Abstract: Structure, method, and computer program for an explicitly tunable device controller. Method supports high-performance I/O without imposing additional overhead during normal input/output operations. Tuning is performed during explicit pre-I/O operation phase. In one embodiment, invention provides a method for tuning device controller operating characteristics to suit attributes of a data stream in which the method comprises: monitoring a data stream and collecting attributes of the monitored data stream; generating performance metrics of the data stream based on the collected attributes and a plurality of different assumed device controller configurations; comparing expected performance of the plurality of different device controller configurations for effectiveness with a future data stream having similar data stream type attributes to the monitored data stream; and selecting device controller characteristics to provide an effective match between the data stream type and the device controller configuration.Type: ApplicationFiled: January 16, 2001Publication date: July 18, 2002Applicant: International Business Machines Corporation:Inventors: Krishnakumar Rao Surugucchi, Bruce M. Cassidy
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Patent number: 6098119Abstract: The present invention pertains to an apparatus and method for automatically configuring disk drives connected to a RAID controller. The automatic configuration mechanism is able to generate a full configuration of the disk drives connected to a RAID controller both at system initialization or bootup and at runtime. The mechanism uses a robust criteria to configure the disk drives which allows the drives to be configured in accordance with one or more RAID levels and which considers any existing configurations. The automatic configuration mechanism is advantageous since it eliminates user interaction, time, and knowledge often required to configure disk drives connected to a RAID controller.Type: GrantFiled: January 21, 1998Date of Patent: August 1, 2000Assignee: Mylex CorporationInventors: Krishnakumar Rao Surugucchi, Kailash
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Patent number: 6094699Abstract: The present invention pertains to an apparatus and method for transparently coupling PCI devices behind a PCI-to-PCI bridge. A controller is coupled to a primary PCI bus and includes a secondary PCI bus that is coupled to the primary PCI bus by a PCI-to-PCI bridge. The secondary PCI bus includes a number of exposed PCI devices that are recognizable by the bridge and a number of hidden PCI devices that are hidden from the bridge. A bridge assist device (BASS) is one such exposed PCI device that is used to acquire a memory address space that is part of the system memory. The memory address space is then partitioned by the controller and assigned to each of the hidden PCI devices. The hidden PCI devices use the memory address space to transmit data to the local CPU. The controller also includes a local-to-PCI bridge that is coupled to the secondary PCI bus and a local bus including a memory and a processor.Type: GrantFiled: February 13, 1998Date of Patent: July 25, 2000Assignee: Mylex CorporationInventors: Krishnakumar Rao Surugucchi, Geeta George