Patents by Inventor Krishnamurthy Dhakshinamurthy
Krishnamurthy Dhakshinamurthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190182954Abstract: A ?SD card is disclosed including an arrangement of interface pins enabling the ?SD card to be used in a combination connector having a slot configured to receive both ?SD cards and SIM cards. In examples, the ?SD card may include multiple rows and/or columns of interface pins configured at positions such that, when the ?SD card is inserted into a multi-card connector, the positions of the ?SD card interface pins do not overlap with the positions of SIM card contacts in the connector.Type: ApplicationFiled: March 16, 2018Publication date: June 13, 2019Applicant: Western Digital Technologies, Inc.Inventors: Shajith Musaliar Sirajudeen, Krishnamurthy Dhakshinamurthy, Taninder Singh Sijher, D. Jegathese, Yosi Pinto, Warren Middlekauff
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Patent number: 10129012Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.Type: GrantFiled: March 29, 2017Date of Patent: November 13, 2018Assignee: SanDisk Technologies LLCInventors: Krishnamurthy Dhakshinamurthy, Shajith Musaliar Sirajudeen, Jayaprakash Naradasi, Bhavin Odedara, Yosi Pinto, Rampraveen Somasundaram, Anand Sharma
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Patent number: 10073627Abstract: A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.Type: GrantFiled: January 13, 2016Date of Patent: September 11, 2018Assignee: SanDisk Technologies LLCInventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Vijay Sivasankaran, Krishnamurthy Dhakshinamurthy, Arun Thandapani
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Publication number: 20180083764Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.Type: ApplicationFiled: March 29, 2017Publication date: March 22, 2018Applicant: SanDisk Technologies LLCInventors: Krishnamurthy Dhakshinamurthy, Shajith Musaliar Sirajudeen, Jayaprakash Naradasi, Bhavin Odedara, Yosi Pinto, Rampraveen Somasundaram, Anand Sharma
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Patent number: 9886080Abstract: A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.Type: GrantFiled: April 28, 2015Date of Patent: February 6, 2018Assignee: SanDisk Technologies LLCInventors: Anil Kumar Thadi Suryaprakash, Krishnamurthy Dhakshinamurthy, Ajay Dhingra, Rampraveen Somasundaram, Narendhiran Chinnaanangur Ravimohan, Bhavin Odedara, Srikanth Bojja, Jayanth Thimmaiah
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Patent number: 9455048Abstract: Systems and methods for improving NAND flash memory yields by identifying memory blocks with benign word line defects. Memory blocks including word line defects may be classified as incomplete memory blocks and may be used for storing data fragments. A data fragment may correspond with data written into memory cells associated with one or more contiguous word lines within a memory block that does not include a bad word line. In some cases, firmware associated with a NAND flash memory device may identify one or more data fragments based on the location of bad word lines within a memory block. A word line defect may be considered a benign defect if the defect does not prevent memory cells connected to other word lines within a memory block from being programmed and/or read reliably.Type: GrantFiled: June 28, 2013Date of Patent: September 27, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Tucker Dean Berckmann, Talal Ahwal, Damian Yurzola, Krishnamurthy Dhakshinamurthy, Yong Peng, Rajeev Nagabhirava, Arjun Hary, Tal Heller, Yigal Eli
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Publication number: 20160202910Abstract: A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.Type: ApplicationFiled: January 13, 2016Publication date: July 14, 2016Applicant: SanDisk Technologies Inc.Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Vijay Sivasankaran, Krishnamurthy Dhakshinamurthy, Arun Thandapani
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Publication number: 20160188245Abstract: A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.Type: ApplicationFiled: April 28, 2015Publication date: June 30, 2016Inventors: Anil Kumar Thadi Suryaprakash, Krishnamurthy Dhakshinamurthy, Ajay Dhingra, Rampraveen Somasundaram, Narendhiran Chinnaanangur Ravimohan
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Publication number: 20150003156Abstract: Methods for improving NAND flash memory yields by identifying memory blocks with benign word line defects are described. Memory blocks including word line defects may be classified as incomplete memory blocks and may be used for storing data fragments. A data fragment may correspond with data written into memory cells associated with one or more contiguous word lines within a memory block that does not include a bad word line. In some cases, firmware associated with a NAND flash memory device may identify one or more data fragments based on the location of bad word lines within a memory block. A word line defect may be considered a benign defect if the defect does not prevent memory cells connected to other word lines within a memory block from being programmed and/or read reliably.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Tucker Dean Berckmann, Talal Ahwal, Damian Yurzola, Krishnamurthy Dhakshinamurthy, Yong Peng, Rajeev Nagabhirava, Arjun Hary, Tal Heller, Yigal Eli
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Publication number: 20140189201Abstract: A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus. The controller is configured to communicate via an N-bit bus. The first and second non-volatile memory chips are configured to communicate via an M-bit bus, with M<N. The system bus connects the controller with the first and second non-volatile memory chips, wherein the system bus is split with some of the system bus lines connected to the first non-volatile memory chip and other of the system bus lines connected to the second non-volatile memory chip. In this way, the controller may communicate command, address and/or data with the memory chips in parallel.Type: ApplicationFiled: March 11, 2013Publication date: July 3, 2014Inventors: Krishnamurthy Dhakshinamurthy, Rajeev Nagabhirava, Tony Ahwal, Leeladhar Agarwal, Piyush Anil Dhotre
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Patent number: 8397018Abstract: Systems and methods for sequentially writing data to a memory device such as a universal serial bus (USB) memory device are disclosed. A system controller of a memory device including a first die and a second die, each of the first die and the second die including a plurality of pages, writes a first portion of a set of data to a lower page of a second die. The system controller then writes a second portion of the set of data to an upper page of the second die after writing the first portion of the set of data to the lower page of the second die.Type: GrantFiled: December 28, 2010Date of Patent: March 12, 2013Assignee: SanDisk Technologies Inc.Inventors: Krishnamurthy Dhakshinamurthy, Damian Yurzola, Rajeev Nagabhirava, Oren Shtrasberg
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Publication number: 20120030412Abstract: Systems and methods for sequentially writing data to a memory device such as a universal serial bus (USB) memory device are disclosed. A system controller of a memory device including a first die and a second die, each of the first die and the second die including a plurality of pages, writes a first portion of a set of data to a lower page of a second die. The system controller then writes a second portion of the set of data to an upper page of the second die after writing the first portion of the set of data to the lower page of the second die.Type: ApplicationFiled: December 28, 2010Publication date: February 2, 2012Inventors: Krishnamurthy Dhakshinamurthy, Damian Yurzola, Rajeev Nagabhirava, Oren Shtrasberg