Patents by Inventor Krishnan Kunjunny Kailas
Krishnan Kunjunny Kailas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9569402Abstract: Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.Type: GrantFiled: April 20, 2012Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan Kunjunny Kailas
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Patent number: 9471535Abstract: Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.Type: GrantFiled: April 20, 2012Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan Kunjunny Kailas
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Patent number: 9442884Abstract: Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.Type: GrantFiled: August 31, 2012Date of Patent: September 13, 2016Assignee: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan Kunjunny Kailas
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Patent number: 9298672Abstract: Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.Type: GrantFiled: September 4, 2012Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan Kunjunny Kailas
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Patent number: 9063807Abstract: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.Type: GrantFiled: August 24, 2012Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Krishnan Kunjunny Kailas, Brian Chan Monwai, Viresh Paruthi
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Publication number: 20130283010Abstract: Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.Type: ApplicationFiled: August 31, 2012Publication date: October 24, 2013Applicant: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan Kunjunny Kailas
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Publication number: 20130283009Abstract: Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan Kunjunny Kailas
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Publication number: 20130283008Abstract: Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan Kunjunny Kailas
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Publication number: 20130283006Abstract: Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image.Type: ApplicationFiled: September 4, 2012Publication date: October 24, 2013Applicant: International Business Machines CorporationInventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan Kunjunny Kailas
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Publication number: 20120323982Abstract: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.Type: ApplicationFiled: August 24, 2012Publication date: December 20, 2012Applicant: International Business Machines CorporationInventors: Krishnan Kunjunny KAILAS, Brian Chan MONWAI, Viresh PARUTHI
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Patent number: 8312071Abstract: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.Type: GrantFiled: April 11, 2008Date of Patent: November 13, 2012Assignee: International Business Machines CorporationInventors: Krishnan Kunjunny Kailas, Brian Chan Monwai, Viresh Paruthi
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Patent number: 8301870Abstract: A method and structure for an out-of-order processor executing at least two threads of instructions that communicate and synchronize with each other. The synchronization is achieved by monitoring addresses of instructions in at least one of the threads.Type: GrantFiled: July 27, 2006Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventor: Krishnan Kunjunny Kailas
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Patent number: 7836256Abstract: One embodiment of the present method and apparatus for application-specific dynamic cache placement includes grouping sets of data in a cache memory system into two or more virtual partitions and processing a load/store instruction in accordance with the virtual partitions, where the load/store instruction specifies at least one of the virtual partitions to which the load/store instruction is assigned.Type: GrantFiled: June 30, 2008Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Krishnan Kunjunny Kailas, Rajiv Alazhath Ravindran, Zehra Sura
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Patent number: 7752369Abstract: A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.Type: GrantFiled: May 9, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Krishnan Kunjunny Kailas, Brian Chan Monwai, Viresh Paruthi
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Patent number: 7665070Abstract: A method (and apparatus) for executing a main program having a series of machine-executable instructions in one of a program binary representation and an object code representation, including establishing a first pipeline for executing the main program and establishing a second pipeline for executing a meta-program to at least one of fetch and store meta-program information of the executing of the main program and a result of an analysis of the executing the main program. The program binary representation or object code representation of the main program is not modified by establishing the second pipeline or by executing the meta-program.Type: GrantFiled: April 23, 2004Date of Patent: February 16, 2010Assignee: International Business Machines CorporationInventor: Krishnan Kunjunny Kailas
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Publication number: 20090282178Abstract: A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence.Type: ApplicationFiled: May 9, 2008Publication date: November 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Krishnan Kunjunny Kailas, Brian Chan Monwai, Viresh Paruthi
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Publication number: 20090259705Abstract: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.Type: ApplicationFiled: April 11, 2008Publication date: October 15, 2009Inventors: Krishnan Kunjunny Kailas, Brian Chan MONWAI, Viresh PARUTHI
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Patent number: 7502890Abstract: One embodiment of the present method and apparatus for dynamic priority-based cache replacement includes selectively assigning relative priority values to at least a subset of data items in the cache memory system, fetching a new data item to load into the cache memory system, the data item being associated with a priority value, and selecting an existing data item from the cache memory system to replace with the new data item, in accordance with the relative priority values and the priority value of the new data item.Type: GrantFiled: July 7, 2006Date of Patent: March 10, 2009Assignee: International Business Machines CorporationInventors: Krishnan Kunjunny Kailas, Rajiv Alazhath Ravindran, Zehra Sura
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Publication number: 20080270705Abstract: One embodiment of the present method and apparatus for application-specific dynamic cache placement includes grouping sets of data in a cache memory system into two or more virtual partitions and processing a load/store instruction in accordance with the virtual partitions, where the load/store instruction specifies at least one of the virtual partitions to which the load/store instruction is assigned.Type: ApplicationFiled: June 30, 2008Publication date: October 30, 2008Inventors: KRISHNAN KUNJUNNY KAILAS, Rajiv Alazhath Ravindran, Zehra Sura
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Publication number: 20080028196Abstract: A method and structure for an out-of-order processor executing at least two threads of instructions that communicate and synchronize with each other. The synchronization is achieved by monitoring addresses of instructions in at least one of the threads.Type: ApplicationFiled: July 27, 2006Publication date: January 31, 2008Inventor: Krishnan Kunjunny Kailas